View STM32F479AI_8915717.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. march 2016 docid028010 rev 3 1/217 stm32f479xx arm ? cortex ? -m4 32b mcu+fpu, 225dmips, up to 2mb flash/384+4kb ram, usb otg hs/fs, ethernet, fmc, dual quad-spi, crypto, graphical accelerator, camera if, lcd-tft & mipi dsi datasheet - production data features ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 180 mhz, mpu, 225 dmips/1.25 dmips/mhz (dhrystone 2.1), and dsp instructions ? memories ? up to 2 mb of flash memory organized into two banks allowing read-while-write ? up to 384+4 kb of sram including 64-kb of ccm (core coupled memory) data ram ? flexible external memory controller with up to 32-bit data bus: sram, psram, sdram/lpsdr, sdram, flash nor/nand memories ? dual-flash mode quad-spi interface ? graphics: ? chrom-art accelerator? (dma2d), graphical hardware accelerator enabling enhanced graphical user interface with minimum cpu load ? lcd parallel interface, 8080/6800 modes ? lcd tft controller supporting up to xga resolution ?mipi ? dsi host controller supporting up to 720p 30hz resolution ? clock, reset and supply management ? 1.7 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? low power ? sleep, stop and standby modes ?v bat supply for rtc, 2032 bit backup registers + optional 4 kb backup sram ? 312-bit, 2.4 msps adc: up to 24 channels and 7.2 msps in triple interleaved mode ? 212-bit d/a converters ? general-purpose dma: 16-stream dma controller with fifos and burst support ? up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 180 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder i nput. 2x watchdogs and systick timer ? debug mode ? swd & jtag interfaces ?cortex ? -m4 trace macrocell? ? up to 161 i/o ports with interrupt capability ? up to 157 fast i/os up to 90 mhz ? up to 159 5 v-tolerant i/os ? up to 21 communica tion interfaces ? up to 3 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts and 4 uarts (11.25 mbit/s, iso7816 interface, lin, irda, modem control) ? up to 6 spis (45 mbits/s), 2 with muxed full- duplex i 2 s for audio class accuracy via internal audio pll or external clock ? 1 x sai (serial audio interface) ? 2 can (2.0b active) ? sdio interface ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full- speed phy and ulpi ? dedicated usb power rail enabling on-chip phys operation throughout the entire mcu power supply range ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii ? 8- to 14-bit parallel camera interface up to 54 mbytes/s ? cryptographic accelerator ? hw accelerator for aes 128 , 192, 256, triple des, hash (md5, sha-1, sha-2) and hmac ? true random number generator ? crc calculation unit ? rtc: subsecond accuracy, hardware calendar ? 96-bit unique id table 1. device summary reference part numbers stm32f479xx STM32F479AI, stm32f479ag, stm32f479bi, stm32f479bg, stm32f479ii, stm32f479ig, stm32f479ni, stm32f479ng, stm32479vg, stm32479vi, stm32479zg, stm32479zi &"'! wlcsp168 ufbga176 (10 x 10 mm) tfbga216 (13 x 13 mm) lqfp100 (14 14 mm) lqfp144 (20 20 mm) lqfp176 (24 24 mm) lqfp208 (28 28 mm) ufbga169 (7 7 mm) www.st.com
contents stm32f479xx 2/217 docid028010 rev 3 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1.1 lqfp176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1.2 lqfp208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1.3 ufbga176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1.4 tfbga216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1 arm ? cortex ? -m4 with fpu and embedded flash and sram . . . . . . . 21 2.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 21 2.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22 2.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.9 flexible memory controller (fmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.10 quad-spi memory interface (quadspi) . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.11 lcd-tft controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.12 dsi host (dsihost) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.13 chrom-art accelerator? (dma2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.14 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 27 2.15 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.16 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.17 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.18 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.19 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.19.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.19.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.20 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.20.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.20.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid028010 rev 3 3/217 stm32f479xx contents 5 2.20.3 regulator on/off and inte rnal reset on/off availability . . . . . . . . . . 34 2.21 real-time clock (rtc), backup sram and backup registers . . . . . . . . . . 35 2.22 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.23 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.24 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.24.1 advanced-control timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.24.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.24.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.24.4 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.24.5 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.24.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.25 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.26 universal synchronous/asynchronous re ceiver transmitters (usart) . . 39 2.27 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.28 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.29 serial audio interface (sai1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.30 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.31 audio and lcd pll(pllsai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.32 secure digital input/output interface (sdio) . . . . . . . . . . . . . . . . . . . . . . . 42 2.33 ethernet mac interface with dedicated dma and ieee 1588 support . . . 42 2.34 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.35 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 43 2.36 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . . . 43 2.37 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.38 cryptographic accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.39 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.40 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.41 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.42 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.43 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.44 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.45 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
contents stm32f479xx 4/217 docid028010 rev 3 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.2 vcap1/vcap2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 95 5.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 95 5.3.5 reset and power control block characterist ics . . . . . . . . . . . . . . . . . . . 95 5.3.6 over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.8 wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.9 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.10 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.3.11 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.3.12 pll spread spectrum clock generatio n (sscg) characteristics . . . . . 122 5.3.13 mipi d-phy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.14 mipi d-phy pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.3.15 mipi d-phy regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.3.16 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.3.17 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.3.18 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 131 5.3.19 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.3.20 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.3.21 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3.22 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.3.23 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.3.24 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
docid028010 rev 3 5/217 stm32f479xx contents 5 5.3.25 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.3.26 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.3.27 reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.3.28 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.3.29 fmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.3.30 quad-spi interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.3.31 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 185 5.3.32 lcd-tft controller (ltdc) characteristics . . . . . . . . . . . . . . . . . . . . . 186 5.3.33 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 188 5.3.34 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.1 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.2 lqfp144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.3 wlcsp168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.4 ufbga169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.5 lqfp176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 6.6 ufbga176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.7 lqfp208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.8 tfbga216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 6.9 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 appendix a recommendations when using inte rnal reset off . . . . . . . . . . . 215 a.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
list of tables stm32f479xx 6/217 docid028010 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f479xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32 table 4. regulator on/off and internal reset on/off availability. . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5. voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 6. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 7. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 8. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 10. stm32f479xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 table 11. fmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 12. alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 13. stm32f479xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 14. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 15. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 16. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 17. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 18. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 94 table 19. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 20. operating conditions at power-up / power-down (r egulator on) . . . . . . . . . . . . . . . . . . . . 95 table 21. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . . 95 table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 23. over-drive switching characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 24. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram, regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 25. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabl ed), regulator on . . . . . . . . . . . . . . 100 table 26. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch), regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 27. typical and maximum current consumption in sleep mode, regulator on. . . . . . . . . . . . 102 table 28. typical and maximum current consumption in sleep mode, regulator of f . . . . . . . . . . . 103 table 29. typical and maximum current consumption in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 104 table 30. typical and maximum current consumption in st andby mode . . . . . . . . . . . . . . . . . . . . . 105 table 31. typical and maximum current consumption in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 106 table 32. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 33. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 34. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 35. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 36. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 37. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 38. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 39. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 40. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 41. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 42. plli2s (audio pll) characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 20 table 43. pllsai (audio and lcd-tft pll) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
docid028010 rev 3 7/217 stm32f479xx list of tables 8 table 44. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 45. mipi d-phy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 46. mipi d-phy ac characteristics lp mode and hs /lp transitions . . . . . . . . . . . . . . . . . . . 125 table 47. dsi-pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 48. dsi regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 49. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 50. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 51. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 52. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 53. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 54. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 55. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 table 56. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 57. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 58. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 59. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 60. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 61. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 62. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 63. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 64. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 65. i 2 s dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 66. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 67. usb otg full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 49 table 68. usb otg full speed dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 69. usb otg full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 70. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 0 table 71. usb hs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 table 72. dynamic characteristics: usb ulpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 73. dynamics characteristics: ethe rnet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . 153 table 74. dynamics characteristics: ethe rnet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . 154 table 75. dynamics characteristics: ethe rnet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 76. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 77. adc static accuracy at f adc = 18 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 78. adc static accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 79. adc static accuracy at f adc = 36 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 80. adc dynamic accuracy at f adc = 18 mhz - limited test conditions . . . . . . . . . . . . . . . . . 158 table 81. adc dynamic accuracy at f adc = 36 mhz - limited test conditions . . . . . . . . . . . . . . . . . 158 table 82. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1 table 83. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 84. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 85. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 86. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 87. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 88. asynchronous non-multiplexed sram/psram/nor - read timings . . . . . . . . . . . . . . . . 166 table 89. asynchronous non-multiplexed sram/psram /nor read - nwait timings . . . . . . . . . . 166 table 90. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 167 table 91. asynchronous non-multiplexed sram/psram/n or write - nwait timings. . . . . . . . . . 168 table 92. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 93. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 169 table 94. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 95. asynchronous multiplexed psram/nor write-nwai t timings . . . . . . . . . . . . . . . . . . . . 171
list of tables stm32f479xx 8/217 docid028010 rev 3 table 96. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 97. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 98. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 176 table 99. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 100. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 101. switching characteristics for nand flash write cycl es. . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 102. sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 103. lpsdr sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 82 table 104. sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 105. lpsdr sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 106. quad-spi characteristics in sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 107. quad-spi characteristics in ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 108. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 109. ltdc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 110. dynamic characteristics: sd / mmc characteri stics, vdd = 2.7 to 3.6 v . . . . . . . . . . . . . 189 table 111. dynamic characteristics: sd / mmc characteri stics, vdd = 1.71 to 1.9 v . . . . . . . . . . . . 190 table 112. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 113. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 114. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 115. wlcsp168 - 168-pin, 4.891 x 5.69 2 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 116. ufbga169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 117. lqfp176, 24 x 24 mm, 176- pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 118. ufbga176+25, - 201-ba ll, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 119. ufbga176+25 recommended pcb design rules (0.65 mm pitch bga) . . . . . . . . . . . . . 206 table 120. lqfp208, 28 x 28 mm, 208- pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 121. tfbga216 - thin fine pitch ball grid array 13 13 0.8mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 122. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 123. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 124. limitations depending on the operating power su pply range . . . . . . . . . . . . . . . . . . . . . . 215 table 125. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
docid028010 rev 3 9/217 stm32f479xx list of figures 11 list of figures figure 1. incompatible board design for lqfp176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 2. incompatible board design for lqfp208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. ufbga176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. tfbga216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. stm32f479xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. stm32f479xx multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 figure 7. vddusb connected to an external independent po wer supply . . . . . . . . . . . . . . . . . . . . . 29 figure 8. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 30 figure 9. pdr_on control with internal re set off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 10. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 , v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 34 figure 12. startup in re gulator off mode: fast v dd slope - power-down reset risen before v cap_1 , v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. stm32f47x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 14. stm32f47x lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 15. stm32f47x wlcsp168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 figure 16. stm32f47x ufbga169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 17. stm32f47x ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 figure 18. stm32f47x lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 19. stm32f47x lqfp208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20. stm32f47x tfbga216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 21. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 22. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 23. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 24. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 25. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 26. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 27. typical v bat current consumption (rtc on / backup sram on and lse in low drive mo de) . . . . . . . . . . . . . . . . . . . . . . 106 figure 28. typical v bat current consumption (rtc on / backup sram on and lse in high drive mode) . . . . . . . . . . . . . . . . . . . . . . 107 figure 29. high-speed external clock source ac timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 30. low-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 31. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 figure 32. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 33. acchsi vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 34. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 35. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 36. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 37. mipi d-phy hs/lp clock lane transition timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 38. mipi d-phy hs/lp data lane transition timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 39. ft i/o input ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 40. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 41. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 42. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 43. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 44. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
list of figures stm32f479xx 10/217 docid028010 rev 3 figure 45. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 46. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 47. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 48. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 49. usb otg full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 150 figure 50. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 51. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 52. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 53. ethernet mii timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 54. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 55. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 56. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 160 figure 57. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 160 figure 58. 12-bit buffered/non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 59. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 165 figure 60. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 167 figure 61. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 168 figure 62. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 170 figure 63. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 64. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 65. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 66. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 67. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 68. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 69. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 179 figure 70. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 180 figure 71. sdram read access waveforms (c l = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 72. sdram write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 figure 73. quad-spi sdr timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 74. quad-spi ddr timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 75. dcmi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 76. lcd-tft horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 87 figure 77. lcd-tft vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 78. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 79. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 80. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 191 figure 81. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 82. lqfp100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 83. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 194 figure 84. lqfp144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 85. lqfp144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 86. wlcsp168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 figure 87. ufbga169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 figure 88. ufbga169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 89. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 201 figure 90. lqfp176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 91. lqfp176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 92. ufbga176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,
docid028010 rev 3 11/217 stm32f479xx list of figures 11 ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 93. ufbga176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footpr int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 94. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 207 figure 95. lqfp208 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 96. lqfp208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 97. tfbga216 - thin fine pitch ball grid array 13 13 0.8mm, package outline . . . . . . . . . 211 figure 98. tfbga216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
description stm32f479xx 12/217 docid028010 rev 3 1 description the stm32f479xx devices are based on the high-performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 180 mhz. the cortex ? -m4 core features a floating point unit (fpu) single precision which supports all arm ? single-precision data- processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the stm32f479xx devices incorporate high-speed embedded memories (flash memory up to 2 mbytes, up to 384 kbytes of sram ), up to 4 kbytes of backup sram, and an extensive range of enhanced i/ os and peripherals connected to two apb buses, two ahb buses and a 32-bit multi-ahb bus matrix. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for mo tor control, two general-purpose 32-bit timers, a true random number generator (rng), and a cryptographic acceleration cell. they also feature standard and advanced communication interfaces: ? up to three i 2 cs ? six spis, two i 2 ss full duplex. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. ? four usarts plus four uarts ? an usb otg full-spee d and a usb otg high- speed with full-speed capability (with the ulpi), ? two cans ? one sai serial audio interface ? an sdmmc host interface ? ethernet and camera interface ? lcd-tft display controller ? chrom-art accelerator? ? dsi host. advanced peripherals include an sdmmc inte rface, a flexible memory control (fmc) interface, a quad-spi flash memory, camera interface for cmos sensors and a cryptographic accelera tion cell. refer to table 2 for the list of peripherals available on each part number. the stm32f479xx devices operate in the ?40 to +105 c temperature range from a 1.7 to 3.6 v power supply. a dedicated supply input for usb (otg_fs and otg_hs) only in full speed mode, is available on all packages. the supply voltage can drop to 1.7 v (refer to section 2.19.2 ). a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f479xx devices are offered in eight packages, ranging from 100 to 216 pins. the set of included peripherals changes with the device chosen, according to table 2 .
docid028010 rev 3 13/217 stm32f479xx description 46 these features make the stm32f479xx microc ontrollers suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances figure 5 shows the general block diagram of the device family. table 2. stm32f479xx features and peripheral counts peripherals stm32f479vx stm32f479zx stm32f479ax stm32f479ix stm32f479bx stm32f479nx flash memory in kbytes 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 sram in kbytes system 384(160+32+128+64) backup 4 fmc memory controller yes quad-spi yes ethernet no yes timers general- purpose 10 advanced- control 2 basic 2 random number generator yes communication interfaces spi / i 2 s 4/2(full duplex) (1) 6/2(full duplex) (1) i 2 c3 usart/uart 4/3 4/4 usb otg fs yes usb otg hs yes can 2 sai 1 sdio yes camera interface yes mipi-dsi host yes lcd-tft yes
description stm32f479xx 14/217 docid028010 rev 3 chrom-art accelerator? (dma2d) yes cryptography yes gpios 71 131 114 131 161 161 12-bit adc number of channels 3 14 20 24 12-bit dac number of channels yes 2 maximum cpu frequency 180 mhz operating voltage 1.7 to 3.6v (2) operating temperatures ambient operating temperature: ? 40 to 85 c / ? 40 to 105 c junction temperature: ? 40 to 105 c / ? 40 to 125 c package lqfp100 lqfp144 ufbga169 wlcsp168 lqfp176 ufbga176 lqfp208 tfbga216 1. the spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio mode. 2. vdd/vdda minimum value of 1.7 v is obtained when the internal reset is off (refer to section 2.19.2 ). table 2. stm32f479xx features and peripheral counts (continued) peripherals stm32f479vx stm32f479zx stm32f479ax stm32f479ix stm32f479bx stm32f479nx
docid028010 rev 3 15/217 stm32f479xx description 46 1.1 compatibility throughout the family stm32f479xx devices are not compatible with other stm32f4xx devices. figure 1 and figure 2 show incompatible board designs, respectively, for lqfp176 and lqfp208 packages (highlighted pins). the ufbga176 and tfbga216 ballouts are compatible with other stm32f4xx devices, only few io port pins are substituted, as shown in figure 3 and figure 4 . the lqfp100, lqfp144 and ufbga169 packages are incompatible with other stm32f4xx devices.
description stm32f479xx 16/217 docid028010 rev 3 1.1.1 lqfp176 package figure 1. incompatible board design for lqfp176 package 1. pins from 85 to 133 are not compatible. 069 966 3, 3, 3, 9'' 966 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9''86% 966 3* 3* 3* 3* 3* 3* 3* 966'6, '6,+267b'1 '6,+267b'3 9'''6, '6,+267b&.1 '6,+267b&.3 966'6, '6,+267b'1 '6,+267b'3 9&$3'6, 9''6, 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 670)[[[[ /4)3 3+ 3% 3% 3% 3% 966 3, 3, 3, 3, 3+ 3+ 3+ 9'' 966 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9'' 966 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 9'' 966 3+ 3+ 3+ 3+ 3+ 670)[[ /4)3 3+
docid028010 rev 3 17/217 stm32f479xx description 46 1.1.2 lqfp208 package figure 2. incompatible board design for lqfp208 package 1. pins from 118 to 128 and pin 137 are not compatible 069 3& 3& 9''86% 9'' 966 966 3* 3* 3* 3* 3* 3* 3* 3* 3* 3* 3* 3* 3* 3* 966'6, 3. '6,+267b'1 3. '6,+267b'3 3. 9'''6, 966 '6,+267b&.1 9'' '6,+267b&.3 3- 966'6, 3- '6,+267b'1 3- '6,+267b'3 3- 9&$3'6, 3- 9'''6, 3- 3' 3' 3' 3' 670)[670)[ /4)3 670)[[[[ /4)3
description stm32f479xx 18/217 docid028010 rev 3 1.1.3 ufbga176 package figure 3. ufbga176 port-to-terminal assignment differences 1. the highlighted pins are substi tuted with dedicated dsi io pi ns on stm32f469xx/479xx devices. '6, +267b '3 '6, +267b '1 '6, +267b &.1 '6, +267b &.3 9&$3 '6, 9'' '6, 9''b 86% 966 '6, '6, +267b '3 '6, +267b '1 9'' '6, 1& 069 $3(3( 3( 3( 3% 3% 3* 3* 3% 3% 3' 3& 3$ 3$ 3$ %3(3( 3( 3% 3% 3% 3* 3* 3* 3* 3' 3' 3& 3& 3$ & 9%$7 3, 3, 3, 3'5 b21 9'' 3* 3' 3' 3, 3$ ' 3& 3, 3, 3, %227 966 966 966 3' 3' 3' 3, 3$ ( 3& 3) 3, 3, 3, 3$ )3& 966 9'' 3+ 966 9&$3 3& 3$ * 3+ 966 9'' 3+ 966 9'' 3& 3& + 3+ 3) 3) 3+ 3* 3& - 15 67 3) 3+ 3* 3* . 3) 3) 3) 9'' 966 3* 3* 3* / 3) %<3$66 b5(* 3' 3* 0966$3& 3) 3& 3& 3& 3% 3* 9&$3 b 3+ 3' 3' 195() 3$ 3$ 3& 3) 3* 9'' 9'' 9'' 3( 3+ 3' 3' 3' 3 3$ 3$ 3$ 3& 3) 3) 3( 3( 3( 3( 3% 3% 3' 3' 5 3$ 3% 3) 3( 3( 3( 3% 3% 3% 3% 966 3$ 9'' 9'' 9'' 9'' 95() 9''$ 3$ 3% 3) 3) 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 3) 3) 3' 3, 3, 3' 3, 3+ 3, 966 9&$3 3& 966 9'' 3& 966 9'' 3* 3* 3* 3* 3' 3' 3+ 3+ 9'' 3+ 3+ 3+ 3+ 3+ 9'' 3' 3, 1& 3' 3, '6, +267b '3 3, 966 9&$3 3& 966 9'' 3& 966 '6, 9''b 86% 3* 3* 3* 3* 3' 3' 9'' '6, '6, +267b '1 9'' '6, 9&$3 '6, '6, +267b &.3 '6, +267b '3 '6, +267b '1 '6, +267b &.1 9'' ^dd??&e???l??? ^dd??&e??le?? ^dd??&e??? ^dd??&e???
docid028010 rev 3 19/217 stm32f479xx description 46 1.1.4 tfbga216 package figure 4. tfbga216 port-to-te rminal assignment differences 1. the highlighted pins are substituted with dedi cated dsi io pins on st m32f469xx/479xx devices. 06y9 $ 3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$ % 3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$ & 9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3, 3, 3$ ' 3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$ ( 3& 3) 3, 3, %227 9'' 9'' 9'' 9'' 9&$3 3+ 3+ 3, 3$ ) 3& 966 3, 9'' 3& 3$ * 3+ 3) 3, 3, 9'' 3& 3& + 3+ 3, 3+ 966 3* 3& - 1567 3) 3+ 3+ 966 9'' 3* 3* . 3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3' 3% 3' / 3) 3& %<3$66 5(* 3% 3' 3' 0 966$ 3* 3' 3' 3* 3* 3- 3+ 1 95() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+ 95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+ 3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3% 3) 3 5 9''$ 3'5 21 3( 3( 3( 9'' 9'' 966 966 966 966 966 966 966 966 966 9'' 3- 3) 9'' 9'' 9'' 9&$3 3' 9'' 3) 3) 3& 3& 3& 3% 3) 9'' 966 3' ^dd??&e???l??? ^dd??&e??le?? ^dd??&e??? ^dd??&e??? 9'' 9'' 3' 9'' 9'' 9'' 3' 9'' 9'' '6, '6, +267b &.3 9''' 86% 966 '6, 9'' '6, '6, +267b &.1 '6, +267b '3 9&$3 '6, '6, +267b '1 '6, +267b '3 '6, +267b '1 3- 9'' 3- 3. 3- 3- 3- 3- 3. 3/ 9''
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docid028010 rev 3 21/217 stm32f479xx functional overview 46 2 functional overview 2.1 arm ? cortex ? -m4 with fpu and embe dded flash and sram the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu core is a 32-bit risc processor that features exceptional code-efficiency, delivering the high-performanc e expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit ) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f47x line is compatible with all arm tools and software. figure 5 shows the general block diagram of the stm32f47x line. note: cortex ? -m4 with fpu core is binary compatible with the cortex ? -m3 core. 2.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator optimized for stm32 industry-standard arm ? cortex ? -m4 with fpu processors. it balances the inherent performance advantage of the arm ? cortex ? -m4 with fpu over flash memory te chnologies, which normally require the processor to wait for the flash memory at higher frequencies. to release the processor full 225 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. based on coremark ? benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 180 mhz. 2.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it.
functional overview stm32f479xx 22/217 docid028010 rev 3 2.4 embedded flash memory the devices embed a flash memory of up to 2 mbytes available for storing programs and data. 2.5 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the c rc calculation unit help s compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.6 embedded sram all devices embed: ? up to 384kbytes of system sram includin g 64 kbytes of ccm (core coupled memory) data ram ram memory is accessed (read/write) at cpu clock speed with 0 wait states. ? 4 kbytes of backup sram this area is accessible only from the cpu. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 2.7 multi-ahb bus matrix the 32-bit multi-ahb bu s matrix interconnects all the ma sters (cpu, dmas, ethernet, usb hs, lcd-tft, and dma2d) and the slaves (flash memory, ram, fmc, quadspi, ahb and apb peripherals) and ensures a seamless and efficien t operation even when several high-speed peripherals work simultaneously.
docid028010 rev 3 23/217 stm32f479xx functional overview 46 figure 6. stm32f479xx multi-ahb matrix 2.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. zd }???rde 'w d 'w d? d ?z?v? h^kd' ,^ ?u??]?r^ /k k > &o?z uu}?? ^zd <?? ^zd? ??<?? ,? ??]?z?o? , ??]?z?o? &d???vo du?o /r? r? ^r? dzw/ dzdd dzdd? dzw? d,zedzd h^z,^zd d^????s d?zd er<?? w w? ^zd? ??<?? >rd&d z?}uzd o??}?~d? >rd&dzd d? y^w/
functional overview stm32f479xx 24/217 docid028010 rev 3 the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? dac ? sdio ? camera interface (dcmi) ? adc ? sai1 ? quadspi. 2.9 flexible memory controller (fmc) the flexible memory controller (fmc) includes three memory controllers: ? the nor/psram memory controller ? the nand/memory controller ? the synchronous dram (sdram/m obile lpsdr sdram) controller the main features of the fmc controller are the following: ? interface with static-memory mapped devices including: ? static random access memory (sram) ? nor flash memory/onenand flash memory ? psram ? nand flash memory with ecc hardware to check up to 8 kbytes of data ? interface with synchronous dram (sdr am/mobile lpsdr sdram) memories ? 8-,16-,32-bit data bus width ? independent chip select control for each memory bank ? independent configuration for each memory bank ? write fifo ? read fifo for sdram controller ? the maximum fmc_clk/fmc_sdclk frequen cy for synchronous accesses is hclk/2. lcd parallel interface the fmc can be configured to interface seam lessly with most grap hic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.
docid028010 rev 3 25/217 stm32f479xx functional overview 46 2.10 quad-spi memory interface (quadspi) all stm32f479xx devices embeds a quad-spi memory interface, which is a specialized communication interface targeting single, dual, quad or dual-flash spi memories. it can work in direct mode through registers, external flash stat us register polling mode and memory mapped mode. up to 256 mbytes external flash memory are mapped, supporting 8, 16 and 32-bit access. code execution is supported. the opcode and the frame format are fully pr ogrammable. communication can be either in single data rate or dual data rate. 2.11 lcd-tft controller the lcd-tft display controller provides a 24-b it parallel digital rgb (red, green, blue) and delivers all signals to interface directly to a broad range of lcd and tft panels up to xga (1024x768) resolution with the following features: ? 2 displays layers with dedicated fifo (64x32-bit) ? color look-up table (clut) up to 256 colors (256x24-bit) per layer ? up to 8 input color formats selectable per layer ? flexible blending between two layers us ing alpha value (per pixel or constant) ? flexible programmable parameters for each layer ? color keying (transparency color) ? up to 4 programmable interrupt events. 2.12 dsi host (dsihost) the dsi host is a dedicated per ipheral for inte rfacing with mipi ? dsi compliant displays. it includes a dedicated video in terface internally connected to the ltdc and a generic apb interface that can be used to transmit information to the display. these interfaces are as follows: ? ltdc interface: ? used to transmit information in video mode, in which the transfers from the host processor to the peripheral take the fo rm of a real-time pixel stream (dpi). ? through a customized for mode, this interf ace can be used to transmit information in full bandwidth in the adapted command mode (dbi). ? apb slave interface: ? allows the transmission of generic information in command mode, and follows a proprietary register interface. ? can operate concurrently with either lt dc interface in either video mode or adapted command mode. ? video mode pattern generator: ? allows the transmission of horizontal/ver tical color bar and d-phy ber testing pattern without any kind of stimuli.
functional overview stm32f479xx 26/217 docid028010 rev 3 the dsi host main features: ? compliant with mipi ? alliance standards ? interface with mipi ? d-phy ? supports all commands defined in the mipi ? alliance specification for dcs: ? transmission of all command mode packets through the apb interface ? transmission of commands in low-power and high-speed during video mode ? supports up to two d-phy data lanes ? bidirectional communication and escape mode support through data lane 0 ? supports non-continuous clock in d-phy clock lane for additional power saving ? supports ultra low-power mode with pll disabled ? ecc and checksum capabilities ? support for end of transmission packet (eotp) ? fault recovery schemes ? 3d transmission support ? configurable selection of system interfaces: ? amba apb for control and optional support for g eneric and dcs commands ? video mode interface through ltdc ? adapted command mode interface through ltdc ? independently programmable virtual channel id in ? video mode ? adapted command mode ? apb slave video mode interfaces features: ? ltdc interface color coding mappings into 24-bit interface: ? 16-bit rgb, configurations 1, 2, and 3 ? 18-bit rgb, configurations 1 and 2 ? 24-bit rgb ? programmable polarity of all ltdc interface signals ? extended resolutions beyond the dpi standard maximum resolution of 800x480 pixels: maximum resolution is limited by available dsi physical link bandwidth: ? number of lanes: 2 ? maximum speed per lane: 500mbps adapted interface features: ? support for sending large amounts of data through the memory_write_start (wms) and memory_write_continue (wmc) dcs commands ? ltdc interface color coding mappings into 24-bit interface: ? 16-bit rgb, configurations 1, 2, and 3 ? 18-bit rgb, configurations 1 and 2 ? 24-bit rgb
docid028010 rev 3 27/217 stm32f479xx functional overview 46 video mode pattern generator: ? vertical and horizontal color bar generation without ltdc stimuli ? ber pattern without ltdc stimuli 2.13 chrom-art accelerator? (dma2d) the chrom-art accelerator? (dma2d) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conv ersion. it supports the following functions: ? rectangle filling with a fixed color ? rectangle copy ? rectangle copy with pixel format conversion ? rectangle composition with blending and pixel format conversion. various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. it embeds dedicated memory to store color lookup tables. an interrupt can be generated when an operation is complete or at a programmed watermark. all the operations are fully automatized and are running independently from the cpu or the dmas. 2.14 nested vectored inter rupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m4 with fpu core. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 2.15 external interrupt/ event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 159 gpios can be connected to the 16 external interrupt lines.
functional overview stm32f479xx 28/217 docid028010 rev 3 2.16 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-tr immed to offer 1% accuracy over the full temperature range . the application can then select as system clo ck either the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a failure is detected, the system automatically switches back to the internal rc oscillator and a software interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 180 mhz. simila rly, full interrupt ma nagement of the pll clock entry is available when necessary (for ex ample if an indirectly us ed external oscillator fails). several prescalers allow t he configuration of the two ahb buses, the high-speed apb (apb2) and the low-sp eed apb (apb1) domains. the maxi mum frequency of the two ahb buses is 180 mhz while th e maximum frequency of the high-speed apb domains is 90 mhz. the maximum allowe d frequency of the low-sp eed apb domain is 45 mhz. the devices embed a dedicated pll (plli2s) and pllsai which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. 2.17 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory through a serial interface. refer to application note an2606 for details. 2.18 power supply schemes ? v dd = 1.7 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. note: v dd /v dda minimum value of 1.7 v is obtained when the internal reset is off (refer to section 2.19.2 ). refer to table 3 to identify the packages supporting this option. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. ? v ddusb can be connected either to vdd or an external independent power supply (3.0 to 3.6v) for usb transceivers. for example, when device is powered at 1. 8v, an independent power supply 3.3v can be connected to v ddusb . when the v ddusb is connected to a separated power supply, it is independent from v dd or v dda but it must be the last supply to be provided and the first to disappear.
docid028010 rev 3 29/217 stm32f479xx functional overview 46 the following conditions must be respected: ? during power-on phase (v dd < v dd_min ), v ddusb should be always lower than v dd ? during power-down phase (v dd < v dd_min ), v ddusb should be always lower than v dd ?v ddusb rising and falling time rate sp ecifications must be respected. ? in operating mode phase, v ddusb could be lower or higher than vdd: ? if usb (usb otg_hs/otg_fs) is used, the associated gpios powered by v ddusb are operating between v ddusb_min and v ddusb_max .the v ddusb supplies both usb transceivers (usb otg_hs and usb otg_fs). ? if only one usb transceiver is used in the application, the gpios associated to the other usb transceiver are still supplied by v ddusb . ? if usb (usb otg_hs/otg_fs) is not used, the associated gpios powered by v ddusb are operating between v dd_min and v dd_max . figure 7. v ddusb connected to an external independent power supply the dsi (display serial interface) sub-system uses several power supply pins which are independent from the other supply pins: ? vdddsi is an independent dsi power supply dedicated for dsi regulator and mipi d- phy. this supply must be connected to global vdd. ? vcapdsi pin is the output of dsi regulator (1.2v) which must be connected externally to vdd12dsi. ? vdd12dsi pin is used to supply the mipi d-phy, and to supply clock and data lanes pins. an external capacitor of 2.2 uf must be connected on vdd12dsi pin. ? vssdsi pin is an isolated supply ground used for dsi sub-system. ? if dsi functionality is not used at all, then: ? vdddsi pin must be connected to global vdd. ? vcapdsi pin must be connected extern ally to vdd12dsi but the external capacitor is no more needed. ? vssdsi pin must be grounded. 069 9 ''86%b0,1 9 ''b0,1 wlph 9 ''86%b0$; 86% ixqfwlrqdoduhd 9 '' 9 ''$ 86%qrq ixqfwlrqdo duhd 9 ''86% 3rzhurq 3rzhugrzq 2shudwlqjprgh 86%qrq ixqfwlrqdo duhd
functional overview stm32f479xx 30/217 docid028010 rev 3 2.19 power supply supervisor 2.19.1 internal reset on on packages embedding the pdr_on pin, th e power supply supervisor is enabled by holding pdr_on high. on the other package, the power supply supervisor is always enabled. the device has an integrated power-on reset (por)/ power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por/pdr is always active and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process star ts, either to confirm or modify default bor thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 2.19.2 internal reset off this feature is available only on packages featuring the pdr_on pin. the internal power-on reset (por) / power-down reset (pdr) circui try is disabled through the pdr_on pin. an external power supply supervisor should monitor v dd and nrst and should maintain the device in reset mode as long as v dd is below a specified threshold. pdr_on must be connected to vss, as shown in figure 8 . figure 8. power supply supervisor interconnection with internal reset off the v dd specified threshold, below which the device must be maintained under reset, is 1.7 v (see figure 9 ). a comprehensive set of power-saving mode allows to design low-power applications. 3'5b21 670)[[ 966 3'5qrwdfwlyh99''9 9%$7 9'' $ssolfdwlrquhvhw vljqdorswlrqdo 06y9
docid028010 rev 3 31/217 stm32f479xx functional overview 46 when the internal reset is off, the following integrated features are no more supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled ? the brownout reset (bor) circuitry must be disabled ? the embedded programmable voltage detector (pvd) is disabled ? v bat functionality is no more available and v bat pin should be connected to v dd . all packages allow to disable the internal reset through the pdr_on signal when connected to vss. figure 9. pdr_on control with internal reset off 1. pdr_on signal to be kept always low. 2.20 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down ? regulator off 2.20.1 regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all ot her packages, the regula tor is always enabled. 069 9 '' wlph 3'5 9 wlph 1567 3'5b21 3'5b21 5hvhwe\rwkhuvrxufhwkdq srzhuvxsso\vxshuylvru
functional overview stm32f479xx 32/217 docid028010 rev 3 there are three power modes configured by software when the regulator is on: ? mr mode used in run/sleep modes or in stop modes ? in run/sleep mode the mr mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. the over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. ? in stop modes the mr can be configured in two ways during stop mode: mr operates in normal mode (default mode of mr in stop mode) mr operates in under-drive mode (reduced leakage mode). ? lpr is used in the stop modes: the lp regulator mode is configured by software when entering stop mode. like the mr mode, the lpr can be configured in two ways during stop mode: ? lpr operates in normal mode (default mode when lpr is on) ? lpr operates in under-drive mode (reduced leakage mode). ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost. refer to table 3 for a summary of voltage regulator modes versus device operating modes. two external ceramic capacitors should be connected on v cap_1 and v cap_2 pin. refer to section 2.18 and table 124 . all packages have the regulator on feature. 2.20.2 regulator off this feature is availa ble only on packages fe aturing the bypass_reg pi n. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v 12 voltage source through v cap_1 and v cap_2 pins. table 3. voltage regulator configuration mode versus device operating mode (1) 1. ?-? means that the corresponding configuration is not available. voltage regulator configuration run mode sleep mode stop mode standby mode normal mode mr mr mr or lpr - over-drive mode (2) 2. the over-drive mode is not available when v dd = 1.7 to 2.1 v. mr mr - - under-drive mode - - mr or lpr - power-down mode ---yes
docid028010 rev 3 33/217 stm32f479xx functional overview 46 since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. refer to operating conditions .the two 2.2 f ceramic capacitors should be replaced by two 100 nf decoupling capacitors. refer to section 2.18 . when the regulator is off, there is no more internal monitoring on v 12 . an external power supply supervisor should be used to monitor the v 12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v 12 power domain. in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin sinc e it allows to reset a part of the v 12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required. ? the over-drive and under-drive modes are not available. ? the standby mode is not available. figure 10. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.7 v, then pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.7 v (see figure 11 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.7 v, then pa0 could be asserted low externally (see figure 12 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application (see operating conditions ). dl9 %<3$66b5(* 9 &$3b 9 &$3b 3$ 9 9 '' 1567 9 '' $ssolfdwlrquhvhw vljqdorswlrqdo ([whuqdo9 &$3b srzhu vxsso\vxshuylvru ([wuhvhwfrqwuroohudfwlyh zkhq9 &$3b 0lq9 9
functional overview stm32f479xx 34/217 docid028010 rev 3 figure 11. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 , v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). figure 12. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 , v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). 2.20.3 regulator on/off and inte rnal reset on/off availability dlj 9 '' wlph 0lq9 3'5 ru9 9 &$3b 9 &$3b 9 1567 wlph 3$ 9 '' wlph 0lq9 9 &$3b 9 &$3b 9 3$ 1567 wlph dli 3'5 ru9 table 4. regulator on/off and in ternal reset on/off availability package regulator on regulator off internal reset on internal reset off wlcsp168 ufbga169 lqfp208 yes no yes pdr_on set to v dd yes pdr_on set to v ss lqfp176 ufbga176 tfbga216 yes bypass_reg set to v ss yes bypass_reg set to v dd
docid028010 rev 3 35/217 stm32f479xx functional overview 46 2.21 real-time clock (rtc), back up sram and backup registers the backup domain includes: ? the real-time clock (rtc) ? 4 kbytes of backup sram ? 20 backup registers the real-time clock (rtc) is an independent bc d timer/counter. dedica ted registers contain the second, minute, hour (in 12/24 hour), we ek day, date, month, year, in bcd (binary- coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensa te for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base cl ock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the 4-kbyte backup sram is an eeprom-like memory area. it can be used to store data which need to be retained in vbat and standby mode. this memory area is disabled by default to minimize power consumption (see section 2.22 ). it can be enabled by software. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 2.22 ). additional 32-bit registers contain the prog rammable alarm subseconds, seconds, minutes, hours, day, and date. like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin.
functional overview stm32f479xx 36/217 docid028010 rev 3 2.22 low-power modes the devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal osc illators are disabled. the voltage regulator can be put either in main regulator mode (mr) or in low-power mode (lpr). both modes can be configured as follows (see table 5 ): ? normal mode (default mode when mr or lpr is enabled) ? under-drive mode. the device can be woken up from the stop mo de by any of the exti line (the exti line source can be one of the 16 external lines , the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. the standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. 2.23 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. table 5. voltage regulator modes in stop mode voltage regulator configuration main regulator (mr) low-power regulator (lpr) normal mode mr on lpr on under-drive mode mr in under-dri ve mode lpr in under-drive mode
docid028010 rev 3 37/217 stm32f479xx functional overview 46 note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is connected to v ss (internal reset off), the v bat functionality is no more available and v bat pin should be connected to v dd . 2.24 timers and watchdogs the devices include two advanced-control time rs, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. table 6 compares the features of the advanced-c ontrol, general-purpose and basic timers. 2.24.1 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable table 6. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max interface clock (mhz) max timer clock (mhz) (1) advanced control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 90 180 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 45 90/180 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 45 90/180 tim9 16-bit up any integer between 1 and 65536 no 2 no 90 180 tim10 , tim11 16-bit up any integer between 1 and 65536 no 1 no 90 180 tim12 16-bit up any integer between 1 and 65536 no 2 no 45 90/180 tim13 , tim14 16-bit up any integer between 1 and 65536 no 1 no 45 90/180 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 45 90/180 1. the maximum timer clock is either 90 or 180 mhz depending on timpre bit configuration in the rcc_dckcfgr register.
functional overview stm32f479xx 38/217 docid028010 rev 3 inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output if configured as standard 16-bit timers, they ha ve the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 and tim8 support indepe ndent dma request generation. 2.24.2 general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f47x devices (see table 6 for differences). ? tim2, tim3, tim4, tim5 the stm32f47x include 4 full-featured g eneral-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers ar e based on a 32-bit auto-reload up/down counter and a 16-bit prescaler. the tim3 an d tim4 timers are based on a 16-bit auto- reload up/down counter and a 16-bit pres caler. they all feature 4 independent channels for input capture/ou tput compare, pwm or one-pul se mode output. this gives up to 16 input capture/output comp are/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanc ed-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have indepen dent dma request generation. they are capable of handling quadrature (incremental ) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10, tim11, ti m12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels fo r input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. 2.24.3 basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support indepe ndent dma request generation. 2.24.4 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the
docid028010 rev 3 39/217 stm32f479xx functional overview 46 main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 2.24.5 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 2.24.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. 2.25 inter-integrated circuit interface (i 2 c) up to three i2c bus interfaces can operate in multimaster and slave modes. they can support the standard (up to 100 khz), and fast (up to 400 khz) modes. they support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. the devices also include programmable analog and digital noise filters (see table 7 ). 2.26 universal synchronous/asynch ronous receiver transmitters (usart) the devices embed four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and four universal asynchronous receiver transmitters (uart4, uart 5, uart7, and uart8). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and u sart6 interfaces are able to communicate at speeds of up to 11.25 mbit/s . the other available in terfaces communicate at up to 5.62 bit/s. table 7. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks
functional overview stm32f479xx 40/217 docid028010 rev 3 usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interf aces can be served by the dma controller. 2.27 serial peripheral interface (spi) the devices feature up to six spis in slave and master modes in full-duplex and simplex communication modes. spi1, spi4, spi5, and spi6 can communicate at up to 45 mbits/s, spi2 and spi3 can communicate at up to 22.5 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card /mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operat e in ti mode for comm unications in master mode and slave mode. table 8. usart feature comparison (1) name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s apb mapping oversampling by 16 oversampling by 8 usart1 x x x x x x 5.62 11.25 apb2 (max. 90 mhz) usart2 x x x x x x 2.81 5.62 apb1 (max. 45 mhz) usart3 x x x x x x 2.81 5.62 apb1 (max. 45 mhz) uart4 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) uart5 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) usart6 x x x x x x 5.62 11.25 apb2 (max. 90 mhz) uart7 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) uart8 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) 1. x = feature supported.
docid028010 rev 3 41/217 stm32f479xx functional overview 46 2.28 inter-integr ated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i2sx can be served by the dma controller. note: for i2s2 full-duplex mode, i2s2_ck and i2s2_ws signals can be used only on gpio port b and gpio port d. 2.29 serial audio interface (sai1) the serial audio interface ( sai1) is based on two independe nt audio sub-blocks which can operate as transmitter or receiver with their fifo. many audio protocols are supported by each block: i2s standards, lsb or msb-justified, pcm/dsp, tdm, ac?97 and spdif output, supporting audio sampling frequencies from 8 khz up to 192 khz. both sub-blocks can be configured in master or in slave mode. in master mode, the master clock can be output to the external dac/codec at 256 times of the sampling frequency. the two sub-blocks can be configured in synchronous mode when full-duplex mode is required. sai1 can be served by the dma controller. 2.30 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s and sai applications. it allows to achieve error-free i 2 s sampling clock accuracy witho ut compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s/sai sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i 2 s/sai flow with an external pll (or codec output). 2.31 audio and lcd pll(pllsai) an additional pll dedicated to audio and lc d-tft is used for sai1 peripheral in case the plli2s is programmed to achieve another audio sampling frequency (49.152 mhz or 11.2896 mhz) and the audio application requi res both sampling frequencies simultaneously. the pllsai is also used to generate the lcd-tft clock.
functional overview stm32f479xx 42/217 docid028010 rev 3 2.32 secure digital input/ output interface (sdio) an sd/sdio/mmc host interface is availabl e, that supports multimediacard system specification version 4.2 in three different da tabus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdi o/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 2.33 ethernet mac interface with dedicated dma and ieee 1588 support the devices provide an ieee- 802.3-2002-compliant media access controller (mac) for ethernet lan communications through an industry-standard medium-independent interface (mii) or a reduced medium-independent interfac e (rmii). the microcontroller requires an external physical interface device (phy) to co nnect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connec ted to the device mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) from the microcontroller. the devices include the following features: ? supports 10 and 100 mbit/s rates ? dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f4xx reference manual for details) ? tagged mac frame support (vlan support) ? half-duplex (csma/cd) and full-duplex operation ? mac control sublayer (control frames) support ? 32-bit crc generation and removal ? several address filtering modes for physic al and multicast address (multicast and group addresses) ? 32-bit status code for each transmitted or received frame ? internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes. ? supports hardware ptp (precision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp compar ator connected to the tim2 input ? triggers interrupt when system time becomes greater than target time 2.34 controller area network (bxcan) the two cans are compliant with the 2.0a and b (a ctive) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit id entifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive
docid028010 rev 3 43/217 stm32f479xx functional overview 46 fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. 2.35 universal serial bus on -the-go full-speed (otg_fs) the device embeds an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg controller requires a dedicat ed 48 mhz clock that is generated by a p ll connected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 1.28 kb with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 1 bidirectional control endpoint + 5 in endpoints + 5 out endpoints ? 12 host channels with periodic out support ? software configurable to otg1.3 and otg2.0 modes of operation ? usb 2.0 lpm (link power management) support ? internal fs otg phy support ? hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.36 universal serial bus on -the-go high-speed (otg_hs) the device embeds a usb otg high-speed (u p to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external phy device connecte d to the ulpi is required. the usb otg hs peripheral is compliant wit h the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg controller requires a dedic ated 48 mhz clock that is generated by a p ll connected to the hse oscillator.
functional overview stm32f479xx 44/217 docid028010 rev 3 the major features are: ? combined rx and tx fifo size of 4 kb with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 8 bidirectional endpoints ? 16 host channels with periodic out support ? software configurable to otg1.3 and otg2.0 modes of operation ? usb 2.0 lpm (link power management) support ? internal fs otg phy support ? external hs or hs otg operation suppor ting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. ? internal usb dma ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.37 digital camera interface (dcmi) the devices embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 54 mbyte/s at 54 mhz. it features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image black & white. 2.38 cryptographic accelerator the devices embed a cryptographic accelerator. this cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data integrity and non repudiation when exchanging messages with a peer. ? these algorithms consists of: encryption/decryption ? des/tdes (data encryption standard/triple data encryption standard): ecb (electronic codebook) and cbc (cipher block chaining) chaining algorithms, 64- ,128- or 192-bit key ? aes (advanced encryption standard): ecb, cbc, gcm, ccm, and ctr (counter mode) chaining algorithms, 128, 192 or 256-bit key
docid028010 rev 3 45/217 stm32f479xx functional overview 46 universal hash ? sha-1 and sha-2 (secure hash algorithms) ?md5 ?hmac the cryptographic accelerator supports dma request generation. 2.39 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit. 2.40 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling a llowing maximum i/o toggling up to 90 mhz. 2.41 analog-to-digital converters (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer. 2.42 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the same input channel as v bat , adc1_in18, which is used to convert the sensor output voltage into a digital value. when the temperature sensor and v bat conversion are enabled at the same time, only v bat conversion is performed.
functional overview stm32f479xx 46/217 docid028010 rev 3 as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.43 digital-to-analog converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 10-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 2.44 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.45 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f47x through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools.
docid028010 rev 3 47/217 stm32f479xx pinouts and pin description 82 3 pinouts and pin description figure 13. stm32f47x lqfp100 pinout 1. the above figure shows the package top view. 069 /4)3 3+ 3& 3& 3& 3& 966$ 95() 9''$ 3$ 3$ 3$ 3$ 966 9'' 3$ 3+ 1567 3& 3& 9'' 3( 966 9%$7 3& 966 3$ 3$ 3% 3( 3( 3$ 3% 3( 3( 3% 3% 3( 3( 9&$3 3% 3( 3( 966 3% 3% 3( 3% 9'' 3% 3' 3& '6,+267b'1 '6,+267b'3 9'''6, '6,+267b&.1 '6,+267b&.3 966'6, '6,+267b'1 '6,+267b'3 9&$3'6, 9'''6, 3' 3' 3' 3' 3& 9''86% 3$ 3$ 3& 3$ 3$ 3$ 3$ 3& 9'' 3% 3% 3% 3' 3% %227 3% 3' 3' 3% 3% 3' 3& 3$ 3' 3' 3& 3$ 9'' 3' 3' 3& 966 9&$3
pinouts and pin description stm32f479xx 48/217 docid028010 rev 3 figure 14. stm32f47x lqfp144 pinout 1. the above figure shows the package top view. 069 /4)3 3& 3& 3& 9'' 966$ 95() 9''$ 3$ 3$ 3$ 3$ 966 9'' 3$ 3$ 1567 3& 966 3) 3+ 3) 3) 9'' 3+ 3$ 3& 3% 3) 3) 3& 3% 9'' 3* 3( 3% 3) 3( 966 3( 3) 3) 9'' 3( 3( 3* 3( 3( 3( 3' '6,+267b'3 '6,+267b&.1 '6,+267b&.3 966'6, '6,+267b'1 '6,+267b'3 9&$3'6, 9'''6, 3' 3' 9'' 966 3' 3' 3' '6,+267b'1 9'''6, 3* 3* 3* 9''86% 3* 3* 3* 3* 3( 9'' 3( %227 3% 3'5b21 3( 3% 3* 3* 3% 3% 9'' 3* 3' 3% 3% 3* 9'' 3' 3% 966 3* 966 3' 3' 3' 3' 3' 3& 3& 3& 966 3$ 9'' 966 9&$3 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3$ 3% 3% 3' 3% 3% 9&$3 3% 9'' 3( 3% 3$ 3) 3) 3& 3& 3) 3( 9%$7 3& 3) 3( 3( 3(
docid028010 rev 3 49/217 stm32f479xx pinouts and pin description 82 figure 15. stm32f47x wlcsp168 pinout 1. the above figure shows the package bottom view. 06y9 3, 9'' 3( 3% 3% 9'' 3* 3' 966 3' 3$ 3, 3( $ % & ' ( ) * + - . / 0 1 3 3, 966 3% 3% 966 3* 9'' 3' 3& 3, 3+ 9%$7 3( 3, 3( 3% 3* 3' 3' 3& 3, 9'' 966 3& 3( 3, 3'5b 21 3* 3* 3' 3& 3$ 3+ 9&$3 3$ 3& 3& 3( 3% 3* 3' 3' 3, 3+ 3$ 3$ 3$ 966 3, 3, 3( %227 3$ 3$ 3& 3& 3& 966 9'' 86% 3) 9'' 3) 3, 3% 3& 3* 3* 3* 3* 3* 3* 3) 3) 3) 1567 3) 966 3* 3% 3' '6, +267 b'3 '6, +267 b'1 966 '6, 9'' 966 3) 3& 3$ 3) 3* 3( 3' '6, +267 b'1 '6, +267 b&.1 '6, +267 b&.3 3+ 3+ 3) 3$ 3+ 3) 3( 3% 3% '6, +267 b'3 9'' '6, 9&$3 '6, 3& 966$ 3$ 3$ 3$ 3) 3( 3+ 3' 3' 3' 9'' '6, 9''$ 3+ 3+ 3$ 3) 3( 3( 3+ 3+ 3' 3' 966 3+ 966 3$ 3% 966 3( 3( 9&$3 3+ 3% 3' 3% 9'' 3$ 3% 3% 9'' 3* 3( 3( 966 9'' 3+ 3%
pinouts and pin description stm32f479xx 50/217 docid028010 rev 3 figure 16. stm32f47x ufbga169 ballout 1. the above figure shows the package top view. 06y9 3, 3$ $ 3, %227 3* 3& 3* 3' 3$ 3( 3( 3$ 3$ 3, 3, % 3( 3% 3' 3& 3* 3' 3$, 3, 3% 3$ 3, 3( 3+ & 3( 3% 3' 3' 3' 3' 3& 3'5b 21 3% 3, 3+ 3( 3* ' 3( 3% 3' 3+ 3% 3$ 9'' 9'' 3% 966 9&$3 3& 3* ( 3, 9%$7 3* 3$ 3* 3$ 3& 966 3, 3* 3* 3& 3* ) 3, 966 9'' 3& 3* 966 3& 3) 9'' 3* 3* 3+ '6, +267b '1 * 3+ 3) 966 966 3( 9'' 3& 3) 3& 9'' 86% '6, +267b '3 '6,b +267 &.1 + 1567 3) 3( 3+ 3( 3+ 3+ 3) 3) 966'6, '6, +267b &.3 3) 966 '6, +267b '1 966$ 3$ 966 3+ 966 3( 966 9''$ 9'' 9'' '6, '6, +267b '3 3$ 9'' '6, . 3$ 3% 3( 3+ 9'' 3( 9'' 3$ 3$ 966'6, 9&$3 '6, 3+ 3' / 3+ 3% 3( 9'' 9'' 3( 3' 3+ 3) 3' 3' 3& 3% 1 3$ 3) 3( 9&$3 3* 3% 3% 3$ 3% 3% 3% 3& 3' 0 3+ 3) 3* 966 3) 3% 3' 3$ 3) 3' 3' -
docid028010 rev 3 51/217 stm32f479xx pinouts and pin description 82 figure 17. stm32f47x ufbga176 ballout 1. the above figure shows the package top view. 069 $3(3( 3( 3 ( 3 % 3% 3* 3* 3% 3% 3' 3& 3$ 3$ 3$ %3(3( 3( 3% 3% 3% 3* 3* 3* 3* 3' 3' 3& 3& 3$ & 9%$7 3, 3, 3, 3'5 b21 3* 3' 3' 3, 1& ' 3& 3, 3, 3, %227 966 966 966 3' 3' 3' 3, 3$ ( 3& 3 ) 3, 3, '6, +267b '3 3, 3$ )3& 966 9'' 3+ 9 66 9&$3 3 & 3$ * 3+ 966 9'' 3+ 966 9'' 3& 3& + 3+ 3) 3) 3+ 966 '6, 9''b 86% 3* 3& - 1567 3) 3+ 3* 3* . 3) 3) 3) 9'' 966 3* 3* 3* / 3) %<3$66 b5(* 3* 0966$3& 3) 3& 3 & 3 & 3% 3* 9&$3 b 3+ 3' 195() 3$ 3$ 3& 3) 3 * 9 '' 9 '' 9 '' 3 + 3 ' 3 ' 3 ' 3 3 $ 3$ 3 $ 3& 3) 3) 3( 3( 3( 3% 3% 3' 3' 5 3$ 3% 3) 3( 3( 3 % 3 % 3 % 966 3$ 9'' '6, '6, +267b '1 9'' '6, 9&$3 '6, '6, +267b &.3 '6, +267b '3 '6, +267b '1 '6, +267b &.1 9'' 9'' 9'' 9'' 95() 9''$ 3$ 3% 3) 3( 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 966 3) 3) 3' 3' 9'' 3$ 3( 3( 3( 3%
pinouts and pin description stm32f479xx 52/217 docid028010 rev 3 figure 18. stm32f47x lqfp176 pinout 1. the above figure shows the package top view. 069 3'5b21 9'' 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3, 3, 3( 3$ 3( 3$ 3( 3( 3$ 3( 3$ 9%$7 3& 3, 3& 3& 3& 3& 3& 3) 9''86% 3) 966 3) 3* 3) 3* 3) 3* 3) 3* 3* 3* 3) 3* 3) 966'6, 3) '6,+267b'1 3) '6,+267b'3 3) 9'''6, 3+ '6,+267b&.1 3+ '6,+267b&.3 1567 966'6, 3& '6,+267b'1 3& '6,+267b'3 3& 9&$3'6, 3& 9'''6, 3' 3' 95() 9'' 966 3$ 3' 3$ 3' 3$ 3' 3$ %<3$66b5(* 9 '' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 3) 3) 3) 3* 3* 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 9&$3b /4)3 3$ 3, 3$ 3$ 9'' 966 3, 3, 3, 3+ 3+ 3+ 3+ 3% 3% 3% 3% 3, 9'' 966 9&$3 3$ 3' 3' 3' 3& 3, 3, 3, 966 3+ 3+ 9'' 966 9'' 9'' 966$ 9''$ 9'' 966 9'' 9''
docid028010 rev 3 53/217 stm32f479xx pinouts and pin description 82 figure 19. stm32f47x lqfp208 pinout 1. the above figure shows the package top view. 06y9 /4)3 3, 3, 3, 3, 9'' 3'5b21 966 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 3. 3. 3. 3. 3. 9'' 966 3* 3* 3* 3* 3* 3* 3- 3- 3- 3- 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 3, 3( 3, 3( 3, 3( 3, 3( 3+ 3( 3+ 9%$7 3+ 3, 9'' 3& 966 3& 9&$3 3& 3$ 3, 3$ 3, 3$ 3, 3$ 966 3$ 9'' 3$ 3) 3& 3) 3& 3) 3& 3, 3& 3, 9''86% 3, 966 3) 3* 3) 3* 3) 3* 966 3* 9'' 3* 3) 3* 3) 3* 3) 966'6, 3) '6,+267b'1 3) '6,+267b'3 3+ 9'''6, 3+ '6,+267b&.1 1567 '6,+267b&.3 3& 966'6, 3& '6,+267b'1 3& '6,+267b'3 3& 9&$3'6, 9'' 9'''6, 966$ 3' 95() 3' 9''$ 9'' 3$ 966 3$ 3' 3$ 3' 3+ 3' 3+ 3' 3+ 3' 3+ 3' 3$ 3% 966 3% 9'' 3% 3$ 3$ 3$ 3$ 3& 3& 9'' 966 3% 3% 3% 3, 3- 3- 3- 3- 3- 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 9&$3 966 9'' 3- 3+ 3+ 3+ 3+ 3+ 3+ 3+ 9'' 3%
pinouts and pin description stm32f479xx 54/217 docid028010 rev 3 figure 20. stm32f47x tfbga216 ballout 1. the above figure shows the package top view. 06y9 $ 3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$ % 3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$ & 9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3, 3, 3$ ' 3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$ ( 3& 3) 3, 3, %227 9'' 9'' 9'' 9'' 9&$3 3+ 3+ 3, 3$ ) 3& 966 3, 9'' 3& 3$ * 3+ 3) 3, 3, 9'' 3& 3& + 3+ 3, 3+ 966 3* 3& - 1567 3) 3+ 3+ 966 9'' 3* 3* . 3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3' 3% 3' / 3) 3& %<3$66 5(* 3% 3' 3' 0 966$ 3* 3' 3' 3* 3* 3- 3+ 1 95() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+ 95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+ 3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3% 3) 3 5 9''$ 9'' '6, '6, +267b &.3 9''' 86% 966 '6, 9'' '6, '6, +267b &.1 '6, +267b '3 3'5 21 9&$3 '6, '6, +267b '1 '6, +267b '3 '6, +267b '1 3( 3( 3( 9'' 9'' 966 966 966 966 966 966 966 966 966 9'' 3- 3) 9'' 9'' 9'' 9&$3 3' 9'' 3) 3) 3& 3& 3& 3% 3) 9'' 966 3'
docid028010 rev 3 55/217 stm32f479xx pinouts and pin description 82 table 9. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tta 3.3 v tolerant i/o directly connected to analog parts b dedicated boot0 pin rst bidirectional reset pin with weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers
pinouts and pin description stm32f479xx 56/217 docid028010 rev 3 table 10. stm32f479xx pin and ball definitions pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216 1 144 b2 f9 a2 1 1 a3 pe2 i/o ft - traceclk, spi4_sck, sai1_mclk_a, quadspi_bk1_io2, eth_mii_txd3, fmc_a23, eventout - nc (2) 1 c1 e10 a1 2 2 a2 pe3 i/o ft - traced0, sai1_sd_b, fmc_a19, eventout - nc (2) 2 c2 c11 b1 3 3 a1 pe4 i/o ft - traced1, spi4_nss, sai1_fs_a, fmc_a20, dcmi_d4, lcd_b0, eventout - nc (2) 3 d1 b12 b2 4 4 b1 pe5 i/o ft - traced2, tim9_ch1, spi4_miso, sai1_sck_a, fmc_a21, dcmi_d6, lcd_g0, eventout - nc (2) 4 d2 d11 b3 5 5 b2 pe6 i/o ft - traced3, tim9_ch2, spi4_mosi, sai1_sd_a, fmc_a22, dcmi_d7, lcd_g1, eventout - 2------g6 vss s-- - - -------f5 vdd s-- - - 3 5 e5 c12 c1 6 6 c1 vbat s - - - - - - - - d2 7 7 c2 pi8 i/o ft (3) (4) eventout rtc_tamp1/ rtc_tamp2/ rtc_ts 4 6g4d12d18 8d1 pc13 i/oft (3) (4) eventout rtc_tamp1/ rtc_ts/ rtc_out 5 7 e1 e11 e1 9 9 e1 pc14-osc32_in (pc14) i/o ft (3) (4) eventout osc32_in 68f1e12f11010f1 pc15- osc32_out (pc15) i/o ft (3) (4) eventout osc32_out -------g5 vdd s-- - - - - e2 g9 d3 11 11 e4 pi9 i/o ft can1_rx, fmc_d30, lcd_vsync, eventout - - - e4 f10 e3 12 12 d5 pi10 i/o ft eth_mii_rx_er, fmc_d31, lcd_hsync, eventout - - - f2 f11 e4 13 13 f3 pi11 i/o ft lcd_g6, otg_hs_ulpi_dir, eventout - - - f5 f12 f2 14 14 f2 vss s - - - - --f4g11f31515f4 vdd s-- - -
docid028010 rev 3 57/217 stm32f479xx pinouts and pin description 82 - 9 f3 g10 e2 16 16 d2 pf0 i/o ft i2c2_sda, fmc_a0, eventout - - 10 g3 h10 h3 17 17 e2 pf1 i/o ft i2c2_scl, fmc_a1, eventout - - 11 g5 g12 h2 18 18 g2 pf2 i/o ft i2c2_smba, fmc_a2, eventout - - - - - - - 19 e3 pi12 i/o ft lcd_hsync, eventout - - - - - - - 20 g3 pi13 i/o ft lcd_vsync, eventout - - - - - - - 21 h3 pi14 i/o ft lcd_clk, eventout - - 12 h4 h11 j2 19 22 h2 pf3 i/o ft (5) fmc_a3, eventout adc3_in9 - 13 l4 j10 j3 20 23 j2 pf4 i/o ft (5) fmc_a4, eventout adc3_in14 - 14 h3 h12 k3 21 24 k3 pf5 i/o ft (5) fmc_a5, eventout adc3_in15 7 15 g7 j11 g2 22 25 h6 vss s - - - - 8 16 g8 j12 g3 23 26 h5 vdd s - - - - - - - - k2 24 27 k2 pf6 i/o ft (5) tim10_ch1, spi5_nss, sai1_sd_b, uart7_rx, quadspi_bk1_io3, eventout adc3_in4 - - - - k1 25 28 k1 pf7 i/o ft (5) tim11_ch1, spi5_sck, sai1_mclk_b, uart7_tx, quadspi_bk1_io2, eventout adc3_in5 - - - - l3 26 29 l3 pf8 i/o ft (5) spi5_miso, sai1_sck_b, tim13_ch1, quadspi_bk1_io0, eventout adc3_in6 - - - - l2 27 30 l2 pf9 i/o ft (5) spi5_mosi, sai1_fs_b, tim14_ch1, quadspi_bk1_io1, eventout adc3_in7 - 17 h1 k10 l1 28 31 l1 pf10 i/o ft (5) quadspi_clk, dcmi_d11, lcd_de, eventout adc3_in8 9 18 g2 k11 g1 29 32 g1 ph0-osc_in (ph0) i/o ft - eventout osc_in 10 19 g1 k12 h1 30 33 h1 ph1-osc_out (ph1) i/o ft - eventout osc_out 11 20 h2 h9 j1 31 34 j1 nrst i/o rst - 12 21 m1 j9 m2 32 35 m2 pc0 i/o ft (5) otg_hs_ulpi_stp, fmc_sdnwe, lcd_r5, eventout adc123_ in10 table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f479xx 58/217 docid028010 rev 3 13 22 n1 l12 m3 33 36 m3 pc1 i/o ft (5) traced0, spi2_mosi/i2s2_sd, sai1_sd_a, eth_mdc, eventout adc123_ in11 14 23 - - m4 34 37 m4 pc2 i/o ft (5) spi2_miso, i2s2ext_sd, otg_hs_ulpi_dir, eth_mii_txd2, fmc_sdne0, eventout adc123_ in12 15 24 - - m5 35 38 l4 pc3 i/o ft (5) spi2_mosi/i2s2_sd, otg_hs_ulpi_nxt, eth_mii_tx_clk, fmc_sdcke0, eventout adc123_ in13 - 25 - - - 36 39 j5 vdd s - - - - -------j6 vss s-- - - 16 26 j2 l11 m1 37 40 m1 vssa s - - - - ----n1--n1 vref- s-- - - 17 27 - - p1 38 41 p1 vref+ s - - - - 18 28 j3 m12 r1 39 42 r1 vdda s - - - - 19 29 j5 l10 n3 40 43 n3 pa0-wkup(pa0) i/o ft (6) tim2_ch1/tim2_etr, tim5_ch1, tim8_etr, usart2_cts, uart4_tx, eth_mii_crs, eventout adc123_in0, wkup 20 30 k1 k9 n2 41 44 n2 pa1 i/o ft (5) tim2_ch2, tim5_ch2, usart2_rts, uart4_rx, quadspi_bk1_io3, eth_mii_rx_clk/eth_r mii_ref_clk, lcd_r2, eventout adc123_in1 21 31 k2 l9 p2 42 45 p2 pa2 i/o ft (5) tim2_ch3, tim5_ch3, tim9_ch1, usart2_tx, eth_mdio, lcd_r1, eventout adc123_in2 - - l2 m11 f4 43 46 k4 ph2 i/o ft - quadspi_bk2_io0, eth_mii_crs, fmc_sdcke0, lcd_r0, eventout - - - l1 n12 g4 44 47 j4 ph3 i/o ft - quadspi_bk2_io1, eth_mii_col, fmc_sdne0, lcd_r1, eventout - - - m2 m10 h4 45 48 h4 ph4 i/o ft - i2c2_scl, lcd_g5, otg_hs_ulpi_nxt, lcd_g4, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
docid028010 rev 3 59/217 stm32f479xx pinouts and pin description 82 - - l3 k8 j4 46 49 j3 ph5 i/o ft - i2c2_sda, spi5_nss, fmc_sdnwe, eventout - 22 32 k3 n10 r2 47 50 r2 pa3 i/o ft (5) tim2_ch4, tim5_ch4, tim9_ch2, usart2_rx, lcd_b2, otg_hs_ulpi_d0, eth_mii_col, lcd_b5, eventout adc123_in3 23 33 j1 n11 - - 51 k6 vss s - - - - - - - - l4 48 - l5 bypass_reg i ft - - - 24 34 j4 p12 k4 49 52 k5 vdd s - - - - 25 35 n2 m9 n4 50 53 n4 pa4 i/o tta - spi1_nss, spi3_nss/i2s3_ws, usart2_ck, otg_hs_sof, dcmi_hsync, lcd_vsync, eventout adc12_in4, dac_out1 26 36 m3 l8 p4 51 54 p4 pa5 i/o tta - tim2_ch1/tim2_etr, tim8_ch1n, spi1_sck, otg_hs_ulpi_ck, lcd_r4, eventout adc12_in5, dac_out2 27 37 n3 p11 p3 52 55 p3 pa6 i/o ft (5) tim1_bkin, tim3_ch1, tim8_bkin, spi1_miso, tim13_ch1, dcmi_pixclk, lcd_g2, eventout adc12_in6 28 38 k4 j8 r3 53 56 r3 pa7 i/o ft (5) tim1_ch1n, tim3_ch2, tim8_ch1n, spi1_mosi, tim14_ch1, quadspi_clk, eth_mii_rx_dv/eth_rmi i_crs_dv, fmc_sdnwe, eventout adc12_in7 nc (2) 39 - - n5 54 57 n5 pc4 i/o ft (5) eth_mii_rxd0/eth_rmii _rxd0, fmc_sdne0, eventout adc12_in14 nc (2) 40 - - p5 55 58 p5 pc5 i/o ft (5) eth_mii_rxd1/eth_rmii _rxd1, fmc_sdcke0, eventout adc12_in15 ------59l7 vdd s-- - - ------60l6 vss s-- - - 29 41 n4 p10 r5 56 61 r5 pb0 i/o ft (5) tim1_ch2n, tim3_ch3, tim8_ch2n, lcd_r3, otg_hs_ulpi_d1, eth_mii_rxd2, lcd_g1, eventout adc12_in8 table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f479xx 60/217 docid028010 rev 3 30 42 k5 n9 r4 57 62 r4 pb1 i/o ft (5) tim1_ch3n, tim3_ch4, tim8_ch3n, lcd_r6, otg_hs_ulpi_d2, eth_mii_rxd3, lcd_g0, eventout adc12_in9 31 43 l5 p9 m6 58 63 m5 pb2- boot1(pb2) i/o ft - eventout - - - - - - - 64 g4 pi15 i/o ft - lcd_g2, lcd_r0, eventout - ------65r6 pj0 i/oft- lcd_r7, lcd_r1, eventout - - - - - - - 66 r7 pj1 i/o ft - lcd_r2, eventout - ------67p7 pj2 i/oft- dsihost_te, lcd_r3, eventout - - - - - - - 68 n8 pj3 i/o ft - lcd_r4, eventout - - - - - - - 69 m9 pj4 i/o ft - lcd_r5, eventout - - 44m5k7r65970p8 pf11 i/oft - spi5_mosi, fmc_sdnras, dcmi_d12, eventout - - 45 n5 m8 p6 60 71 m6 pf12 i/o ft - fmc_a6, eventout - - - j6 n8 m8 61 72 k7 vss s - - - - - 46k6p8n86273l8 vdd s - - - - - 47m4j7n66374n6 pf13 i/oft - fmc_a7, eventout - - 48h5l7r76475p6 pf14 i/oft - fmc_a8, eventout - - 49m6h8p76576m8 pf15 i/oft - fmc_a9, eventout - - 50n6j6n76677n7 pg0 i/oft - fmc_a10, eventout - - 51m7p7m76778m7 pg1 i/oft - fmc_a11, eventout - 32 52 n7 n7 r8 68 79 r8 pe7 i/o ft - tim1_etr, uart7_rx, quadspi_bk2_io0, fmc_d4, eventout - 33 53 g6 m7 p8 69 80 n9 pe8 i/o ft - tim1_ch1n, uart7_tx, quadspi_bk2_io1, fmc_d5, eventout - 34 54 h6 k6 p9 70 81 p9 pe9 i/o ft - tim1_ch1, quadspi_bk2_io2, fmc_d6, eventout - - 55 j7 - m9 71 82 k8 vss s - - - - - 56 l6 - n9 72 83 l9 vdd s - - - - 35 57 h7 p6 r9 73 84 r9 pe10 i/o ft - tim1_ch2n, quadspi_bk2_io3, fmc_d7, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
docid028010 rev 3 61/217 stm32f479xx pinouts and pin description 82 36 58 k7 n6 p10 74 85 p10 pe11 i/o ft - tim1_ch2, spi4_nss, fmc_d8, lcd_g3, eventout - 37 59 l7 m6 r10 75 86 r10 pe12 i/o ft - tim1_ch3n, spi4_sck, fmc_d9, lcd_b4, eventout - 38 60 j8 l6 n11 76 87 r12 pe13 i/o ft - tim1_ch3, spi4_miso, fmc_d10, lcd_de, eventout - 39 61 k8 j5 p11 77 88 p11 pe14 i/o ft - tim1_ch4, spi4_mosi, fmc_d11, lcd_clk, eventout - 40 62 l8 p5 r11 78 89 r11 pe15 i/o ft - tim1_bkin, fmc_d12, lcd_r7, eventout - 41 63 m8 n5 r12 79 90 p12 pb10 i/o ft - tim2_ch3, i2c2_scl, spi2_sck/i2s2_ck, usart3_tx, quadspi_bk1_ncs, otg_hs_ulpi_d3, eth_mii_rx_er, lcd_g4, eventout - 42 64 n8 k5 r13 80 91 r13 pb11 i/o ft - tim2_ch4, i2c2_sda, usart3_rx, otg_hs_ulpi_d4, eth_mii_tx_en/eth_rmi i_tx_en, dsihost_te, lcd_g5, eventout - 43 65 n9 n4 m10 81 92 l11 vcap1 s - - - - 44 - m9 p4 - - 93 k9 vss s - - - - 45 66 l9 p3 n10 82 94 l10 vdd s - - - - - - - - - - 95 m14 pj5 i/o ft - lcd_r6, eventout - - - - - m11 83 96 p13 ph6 i/o ft - i2c2_smba, spi5_sck, tim12_ch1, eth_mii_rxd2, fmc_sdne1, dcmi_d8, eventout - - - - - n12 84 97 n13 ph7 i/o ft - i2c3_scl, spi5_miso, eth_mii_rxd3, fmc_sdcke1, dcmi_d9, eventout - - - h8 m5 - - 98 p14 ph8 i/o ft - i2c3_sda, fmc_d16, dcmi_hsync, lcd_r2, eventout - - - h9 l5 - - 99 n14 ph9 i/o ft - i2c3_smba, tim12_ch2, fmc_d17, dcmi_d0, lcd_r3, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f479xx 62/217 docid028010 rev 3 - - j9 m4 - - 100 p15 ph10 i/o ft - tim5_ch1, fmc_d18, dcmi_d1, lcd_r4, eventout - - - k9 n3 - - 101 n15 ph11 i/o ft - tim5_ch2, fmc_d19, dcmi_d2, lcd_r5, eventout - - - h10 p2 - - 102 m15 ph12 i/o ft - tim5_ch3, fmc_d20, dcmi_d3, lcd_r6, eventout - ---h7---k10 vss s-- - - -66----103k11 vdd s-- - - 46 67 n10 h5 p12 85 104 l13 pb12 i/o ft - tim1_bkin, i2c2_smba, spi2_nss/i2s2_ws, usart3_ck, can2_rx, otg_hs_ulpi_d5, eth_mii_txd0/eth_rmii _txd0, otg_hs_id, eventout - 47 68 n11 k4 p13 86 105 k14 pb13 i/o ft - tim1_ch1n, spi2_sck/i2s2_ck, usart3_cts, can2_tx, otg_hs_ulpi_d6, eth_mii_txd1/eth_rmii _txd1, eventout otg_hs_ vbus 48 69 n12 p1 r14 87 106 r14 pb14 i/o ft - tim1_ch2n, tim8_ch2n, spi2_miso, i2s2ext_sd, usart3_rts, tim12_ch1, otg_hs_dm, eventout - 49 70 n13 n2 r15 88 107 r15 pb15 i/o ft - rtc_refin, tim1_ch3n, tim8_ch3n, spi2_mosi/i2s2_sd, tim12_ch2, otg_hs_dp, eventout - 50 71 l10 l4 p15 89 108 l15 pd8 i/o ft - usart3_tx, fmc_d13, eventout - 51 72 m10 n1 p14 90 109 l14 pd9 i/o ft - usart3_rx, fmc_d14, eventout - 52 73 l11 m3 n15 91 110 k15 pd10 i/o ft - usart3_ck, fmc_d15, lcd_b3, eventout - - 74 m11 j4 n14 92 111 n10 pd11 i/o ft - usart3_cts, quadspi_bk1_io0, fmc_a16/fmc_cle, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
docid028010 rev 3 63/217 stm32f479xx pinouts and pin description 82 - 75 m13 m2 n13 93 112 m10 pd12 i/o ft - tim4_ch1, usart3_rts, quadspi_bk1_io1, fmc_a17/fmc_ale, eventout - - - m12 h4 m15 94 113 m11 pd13 i/o ft - tim4_ch2, quadspi_bk1_io3, fmc_a18, eventout - - 76 j10 m1 - 95 114 j10 vss s - - - - - 77 k10 - j13 96 115 j11 vdd s - - - - 53 78 l12 l3 m14 97 116 l12 pd14 i/o ft - tim4_ch3, fmc_d0, eventout - 54 79 l13 l2 l14 98 117 k13 pd15 i/o ft - tim4_ch4, fmc_d1, eventout - 55 80 k13 l1 j12 99 118 h11 vdddsi s - - - - -------h10 vss s-- - - 56 81 k12 k1 k12 100 119 k12 vcapdsi s - - - - - - - k2 d13 - - g13 vdd12dsi s - - - - 57 82 j12 k3 m12 101 120 j12 dsihost_d0p i/o - - - - 58 83 j13 j3 m13 102 121 j13 dsihost_d0n i/o - - - - 59 84 k11 h1 h12 103 122 g12 vssdsi s - - - - 60 85 h12 j1 l12 104 123 h12 dsihost_ckp i/o - - - - 61 86 h13 j2 l13 105 124 h13 dsihost_ckn i/o - - - - 62 87 j11 - d13 106 125 - vdd12dsi s - - - - 63 88 g12 h3 e12 107 126 f12 dsihost_d1p i/o - - - - 64 89 g13 h2 e13 108 127 f13 dsihost_d1n i/o - - - - - - h11 - h12 109 128 - vssdsi s - - - - - 90 f13 g5 l15 110 129 m13 pg2 i/o ft - fmc_a12, eventout - - 91 f12 g4 k15 111 130 m12 pg3 i/o ft - fmc_a13, eventout - - 92 e13 g2 k14 112 131 n12 pg4 i/o ft - fmc_a14/fmc_ba0, eventout - - 93 e12 g1 k13 113 132 n11 pg5 i/o ft - fmc_a15/fmc_ba1, eventout - - 94 f11 g3 j15 114 133 j15 pg6 i/o ft - dcmi_d12, lcd_r7, eventout - - 95 e11 h6 j14 115 134 j14 pg7 i/o ft - sai1_mclk_a, usart6_ck, fmc_int, dcmi_d13, lcd_clk, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f479xx 64/217 docid028010 rev 3 - 96 d13 g6 h14 116 135 h14 pg8 i/o ft - spi6_nss, usart6_rts, eth_pps_out, fmc_sdclk, lcd_g7, eventout - - - g9 f2 g12 117 136 g10 vss s - - - - 65 97 g11 f1 h13 118 137 g11 vddusb s - - - - 66 98 f9 f3 h15 119 138 h15 pc6 i/o ft - tim3_ch1, tim8_ch1, i2s2_mck, usart6_tx, sdio_d6, dcmi_d0, lcd_hsync, eventout - 67 99 f10 g7 g15 120 139 g15 pc7 i/o ft - tim3_ch2, tim8_ch2, i2s3_mck, usart6_rx, sdio_d7, dcmi_d1, lcd_g6, eventout - 68 100 e10 f4 g14 121 140 g14 pc8 i/o ft - traced1, tim3_ch3, tim8_ch3, usart6_ck, sdio_d0, dcmi_d2, eventout - 69 101 g10 f5 f14 122 141 f14 pc9 i/o ft - mco2, tim3_ch4, tim8_ch4, i2c3_sda, i2s_ckin, quadspi_bk1_io0, sdio_d1, dcmi_d3, eventout - 70 102 d8 e1 f15 123 142 f15 pa8 i/o ft - mco1, tim1_ch1, i2c3_scl, usart1_ck, otg_fs_sof, lcd_r6, eventout - 71 103 e8 e2 e15 124 143 e15 pa9 i/o ft - tim1_ch2, i2c3_smba, spi2_sck/i2s2_ck, usart1_tx, dcmi_d0, eventout otg_fs_ vbus 72 104 e9 e3 d15 125 144 d15 pa10 i/o ft - tim1_ch3, usart1_rx, otg_fs_id, dcmi_d1, eventout - 73 105 a13 f7 c15 126 145 c15 pa11 i/o ft - tim1_ch4, usart1_cts, can1_rx, otg_fs_dm, lcd_r4, eventout - 74 106 a12 f6 b15 127 146 b15 pa12 i/o ft - tim1_etr, usart1_rts, can1_tx, otg_fs_dp, lcd_r5, eventout - 75 107 a11 d1 a15 128 147 a15 pa13(jtms- swdio) i/o ft - jtms-swdio, eventout - 76 108 d12 d2 f13 129 148 e11 vcap2 s - - - - - 109 d11 c1 f12 130 149 f10 vss s - - - - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
docid028010 rev 3 65/217 stm32f479xx pinouts and pin description 82 77 110 d10 c2 g13 131 150 f11 vdd s - - - - - - d9 b1 - - 151 e12 ph13 i/o ft - tim8_ch1n, can1_tx, fmc_d21, lcd_g2, eventout - - - c13 d3 - - 152 e13 ph14 i/o ft - tim8_ch2n, fmc_d22, dcmi_d4, lcd_g3, eventout - - - c12 e4 - - 153 d13 ph15 i/o ft - tim8_ch3n, fmc_d23, dcmi_d11, lcd_g4, eventout - - - b13 e5 e14 132 154 e14 pi0 i/o ft - tim5_ch4, spi2_nss/i2s2_ws (7) , fmc_d24, dcmi_d13, lcd_g5, eventout - - - c11 c3 d14 133 155 d14 pi1 i/o ft - spi2_sck/i2s2_ck (7) , fmc_d25, dcmi_d8, lcd_g6, eventout - --b12a1- nc (2) 156 c14 pi2 i/o ft - tim8_ch4, spi2_miso, i2s2ext_sd, fmc_d26, dcmi_d9, lcd_g7, eventout - - - b10 b2 c13 134 157 c13 pi3 i/o ft - tim8_etr, spi2_mosi/i2s2_sd, fmc_d27, dcmi_d10, eventout - 78 - - - d9 135 - f9 vss s - - - - - - - b5 c9 136 158 e10 vdd s - - - - 79 111 a10 d4 a14 137 159 a14 pa14(jtck- swclk) i/o ft - jtck-swclk, eventout - 80 112 b11 a2 a13 138 160 a13 pa15(jtdi) i/o ft - jtdi, tim2_ch1/tim2_etr, spi1_nss, spi3_nss/i2s3_ws, eventout - 81 113 c10 d5 b14 139 161 b14 pc10 i/o ft - spi3_sck/i2s3_ck, usart3_tx, uart4_tx, quadspi_bk1_io1, sdio_d2, dcmi_d8, lcd_r2, eventout - 82 114 b9 b3 b13 140 162 b13 pc11 i/o ft - i2s3ext_sd, spi3_miso, usart3_rx, uart4_rx, quadspi_bk2_ncs, sdio_d3, dcmi_d4, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f479xx 66/217 docid028010 rev 3 83 115 a9 c4 a12 141 163 a12 pc12 i/o ft - traced3, spi3_mosi/i2s3_sd, usart3_ck, uart5_tx, sdio_ck, dcmi_d9, eventout - 84 116 c9 e6 b12 142 164 b12 pd0 i/o ft - can1_rx, fmc_d2, eventout - 85 117 c7 a3 c12 143 165 c12 pd1 i/o ft - can1_tx, fmc_d3, eventout - 86 118 b8 c5 d12 144 166 d12 pd2 i/o ft - traced2, tim3_etr, uart5_rx, sdio_cmd, dcmi_d11, eventout - 87 119 c8 d6 d11 145 167 c11 pd3 i/o ft - spi2_sck/i2s2_ck, usart2_cts, fmc_clk, dcmi_d5, lcd_g7, eventout - 88 120 c6 b4 d10 146 168 d11 pd4 i/o ft - usart2_rts, fmc_noe, eventout - 89 121 b7 c6 c11 147 169 c10 pd5 i/o ft - usart2_tx, fmc_nwe, eventout - - 122 f8 a4 d8 148 170 f8 vss s - - - - - 123 f7 - c8 149 171 e9 vdd s - - - - 90 124 d7 e7 b11 150 172 b11 pd6 i/o ft - spi3_mosi/i2s3_sd, sai1_sd_a, usart2_rx, fmc_nwait, dcmi_d10, lcd_b2, eventout - 91 - a8 a5 a11 151 173 a11 pd7 i/o ft - usart2_ck, fmc_ne1, eventout - ------174b10 pj12 i/oft- lcd_g3, lcd_b0, eventout - - - - - - - 175 b9 pj13 i/o ft - lcd_g4, lcd_b1, eventout - - - - - - - 176 c9 pj14 i/o ft - lcd_b2, eventout - - - - - - - 177 d10 pj15 i/o ft - lcd_b3, eventout - - 125 e6 d7 c10 152 178 d9 pg9 i/o ft - usart6_rx, quadspi_bk2_io2, fmc_ne2/fmc_nce, dcmi_vsync, eventout - - 126 e7 c7 b10 153 179 c8 pg10 i/o ft - lcd_g3, fmc_ne3, dcmi_d2, lcd_b2, eventout - - 127 b6 b6 b9 154 180 b8 pg11 i/o ft - eth_mii_tx_en/eth_rmi i_tx_en, dcmi_d3, lcd_b3, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
docid028010 rev 3 67/217 stm32f479xx pinouts and pin description 82 - 128 a7 a6 b8 155 181 c7 pg12 i/o ft - spi6_miso, usart6_rts, lcd_b4, fmc_ne4, lcd_b1, eventout - - - a6 e8 a8 156 182 b3 pg13 i/o ft - traced0, spi6_sck, usart6_cts, eth_mii_txd0/eth_rmii _txd0, fmc_a24, lcd_r0, eventout - - - - - a7 157 183 a4 pg14 i/o ft - traced1, spi6_mosi, usart6_tx, quadspi_bk2_io3, eth_mii_txd1/eth_rmii _txd1, fmc_a25, lcd_b0, eventout - - 129 - b7 d7 158 184 f7 vss s - - - - - 130 - a7 c7 159 185 e8 vdd s - - - - - - - - - - 186 d8 pk3 i/o ft - lcd_b4, eventout - - - - - - - 187 d7 pk4 i/o ft - lcd_b5, eventout - - - - - - - 188 c6 pk5 i/o ft - lcd_b6, eventout - - - - - - - 189 c5 pk6 i/o ft - lcd_b7, eventout - - - - - - - 190 c4 pk7 i/o ft - lcd_de, eventout - - 131 f6 d8 b7 160 191 b7 pg15 i/o ft - usart6_cts, fmc_sdncas, dcmi_d13, eventout - 92 132 b5 a8 a10 161 192 a10 pb3(jtdo/tra ceswo) i/o ft - jtdo/traceswo, tim2_ch2, spi1_sck, spi3_sck/i2s3_ck, eventout - 93 133 d6 c8 a9 162 193 a9 pb4(njtrst) i/o ft - njtrst, tim3_ch1, spi1_miso, spi3_miso, i2s3ext_sd, eventout - 94 134 d5 b8 a6 163 194 a8 pb5 i/o ft - tim3_ch2, i2c1_smba, spi1_mosi, spi3_mosi/i2s3_sd, can2_rx, otg_hs_ulpi_d7, eth_pps_out, fmc_sdcke1, dcmi_d10, lcd_g7, eventout - 95 135 c5 g8 b6 164 195 b6 pb6 i/o ft - tim4_ch1, i2c1_scl, usart1_tx, can2_tx, quadspi_bk1_ncs, fmc_sdne1, dcmi_d5, eventout - table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f479xx 68/217 docid028010 rev 3 96 136 b4 a9 b5 165 196 b5 pb7 i/o ft - tim4_ch2, i2c1_sda, usart1_rx, fmc_nl, dcmi_vsync, eventout - 97 137 a5 f8 d6 166 197 e6 boot0 i b - - vpp 98 138 d4 b9 a5 167 198 a7 pb8 i/o ft - tim4_ch3, tim10_ch1, i2c1_scl, can1_rx, eth_mii_txd3, sdio_d4, dcmi_d6, lcd_b6, eventout - 99 139 c4 e9 b4 168 199 b4 pb9 i/o ft - tim4_ch4, tim11_ch1, i2c1_sda, spi2_nss/i2s2_ws, can1_tx, sdio_d5, dcmi_d7, lcd_b7, eventout - nc (2) 140 a4 a10 a4 169 200 a6 pe0 i/o ft - tim4_etr, uart8_rx, fmc_nbl0, dcmi_d2, eventout - nc (2) 141 a3 c9 a3 170 201 a5 pe1 i/o ft - uart8_tx, fmc_nbl1, dcmi_d3, eventout - - - e3 b10 d5 - 202 f6 vss s - - - - - 142 c3 d9 c6 171 203 e5 pdr_on s - - - - 100 143 d3 a11 c5 172 204 e7 vdd s - - - - - - b3 d10 d4 173 205 c3 pi4 i/o ft - tim8_bkin, fmc_nbl2, dcmi_d5, lcd_b4, eventout - - - a2 c10 c4 174 206 d3 pi5 i/o ft - tim8_ch1, fmc_nbl3, dcmi_vsync, lcd_b5, eventout - - - a1 b11 c3 175 207 d6 pi6 i/o ft - tim8_ch2, fmc_d28, dcmi_d6, lcd_b6, eventout - - - b1 a12 c2 176 208 d4 pi7 i/o ft - tim8_ch3, fmc_d29, dcmi_d7, lcd_b7, eventout - 1. function availability depends on the chosen device. 2. nc (not-connected) pins are not bonded. they must be configur ed by software to output push-pull and forced to ?0? in the output data register to avoid extra cu rrent consumption in low power modes. 3. pc13, pc14, pc15 and pi8 are supplied through the power switch . since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a current source (e.g. to drive an led). 4. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main rese t). for details on how to manage these i/os, refer to the rtc register description sections in the stm32f4xx reference manual, available from the stmicroelectronics website: www.st.com. 5. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). table 10. stm32f479xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin types i/o structures notes alternate functions additional functions lqfp100 lqfp144 ufbga169 wlcsp168 ufbga176 lqfp176 lqfp208 tfbga216
docid028010 rev 3 69/217 stm32f479xx pinouts and pin description 82 6. if the device is delivered in an wlcsp168, ufbga169 , ufbga176, lqfp176 or tfbga216 package, and the bypass_reg pin is set to vdd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low). 7. pi0 and pi1 cannot be used for i2s2 full-duplex mode.
pinouts and pin description stm32f479xx 70/217 docid028010 rev 3 table 11. fmc pin definition pin name nor/psram/sram nor/psram mux nand16 sdram pf0 a0 - - a0 pf1 a1 - - a1 pf2 a2 - - a2 pf3 a3 - - a3 pf4 a4 - - a4 pf5 a5 - - a5 pf12 a6 - - a6 pf13 a7 - - a7 pf14 a8 - - a8 pf15 a9 - - a9 pg0 a10 - - a10 pg1 a11 - - a11 pg2 a12 - - a12 pg3 a13 - - pg4 a14 - - ba0 pg5 a15 - - ba1 pd11 a16 a16 cle - pd12 a17 a17 ale - pd13 a18 a18 - - pe3 a19 a19 - - pe4 a20 a20 - - pe5 a21 a21 - - pe6 a22 a22 - - pe2 a23 a23 - - pg13 a24 a24 - - pg14 a25 a25 - - pd14 d0 da0 d0 d0 pd15 d1 da1 d1 d1 pd0 d2 da2 d2 d2 pd1 d3 da3 d3 d3 pe7 d4 da4 d4 d4 pe8 d5 da5 d5 d5 pe9 d6 da6 d6 d6 pe10 d7 da7 d7 d7 pe11 d8 da8 d8 d8
docid028010 rev 3 71/217 stm32f479xx pinouts and pin description 82 pe12 d9 da9 d9 d9 pe13 d10 da10 d10 d10 pe14 d11 da11 d11 d11 pe15 d12 da12 d12 d12 pd8 d13 da13 d13 d13 pd9 d14 da14 d14 d14 pd10 d15 da15 d15 d15 ph8 d16 - - d16 ph9 d17 - - d17 ph10 d18 - - d18 ph11 d19 - - d19 ph12 d20 - - d20 ph13 d21 - - d21 ph14 d22 - - d22 ph15 d23 - - d23 pi0 d24 - - d24 pi1 d25 - - d25 pi2 d26 - - d26 pi3 d27 - - d27 pi6 d28 - - d28 pi7 d29 - - d29 pi9 d30 - - d30 pi10 d31 - - d31 pd7 ne1 ne1 - - pg9 ne2 ne2 nce - pg10 ne3 ne3 - - pg11 - - - - pg12 ne4 ne4 - - pd3 clk clk - - pd4 noe noe noe - pd5 nwe nwe nwe - pd6 nwait nwait nwait - pb7 nadv nadv - - pf6 - - - - pf7 - - - - table 11. fmc pin definition (continued) pin name nor/psram/sram nor/psram mux nand16 sdram
pinouts and pin description stm32f479xx 72/217 docid028010 rev 3 pf8 - - - - pf9 - - - - pf10 - - - - pg6 - - - - pg7 - - int - pe0 nbl0 nbl0 - nbl0 pe1 nbl1 nbl1 - nbl1 pi4 nbl2 - - nbl2 pi5 nbl3 - - nbl3 pg8 - - - sdclk pc0 - - - sdnwe pf11 - - - sdnras pg15 - - - sdncas ph2 - - - sdcke0 ph3 - - - sdne0 ph6 - - - sdne1 ph7 - - - sdcke1 ph5 - - - sdnwe pc2 - - - sdne0 pc3 - - - sdcke0 pb5 - - - sdcke1 pb6 - - - sdne1 table 11. fmc pin definition (continued) pin name nor/psram/sram nor/psram mux nand16 sdram
stm32f479xx pinouts and pin description docid028010 rev 3 73/217 table 12. alternate function port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys port a pa0 - tim2_ch1/ tim2_etr tim5_ch1 tim8_etr - - - usart2_ cts uart4_ tx - - eth_mii_crs - - - event out pa1 - tim2_ch2 tim5_ch2 -- -- usart2_ rts uart4_ rx quadspi_ bk1_io3 - eth_mii_rx_ clk/eth_rmi i_ref_clk -- lcd_r2 event out pa2 - tim2_ch3 tim5_ch3 tim9_ch1 --- usart2_t x -- - eth_mdio -- lcd_r1 event out pa3 - tim2_ch4 tim5_ch4 tim9_ch2 --- usart2_ rx - lcd_b2 otg_hs _ulpi_d0 eth_mii_col -- lcd_b5 event out pa4 -- - - - spi1_nss spi3_nss/ i2s3_ws usart2_ ck -- - - otg_hs_s of dcmi_hs ync lcd_vsy nc event out pa5 - tim2_ch1/ tim2_etr - tim8_ch1 n - spi1_sck ---- otg_hs _ulpi_c k - - - lcd_r4 event out pa6 - tim1_bkin tim3_ch1 tim8_bki n - spi1_ miso --- tim13_ch1 - - - dcmi_pix clk lcd_g2 event out pa7 - tim1_ ch1n tim3_ch2 tim8_ch1 n - spi1_ mosi --- tim14_ch1 quadspi _clk eth_mii_rx_ dv/eth_rmii _crs_dv fmc_sdn we -- event out pa8 mco1 tim1_ch1 -- i2c3_scl - - usart1_ ck -- otg_fs_ sof --- lcd_r6 event out pa9 - tim1_ch2 -- i2c3_smba spi2_sck/i 2s2_ck - usart1_t x -- - - - dcmi_d0 - event out pa10 - tim1_ch3 -- - - - usart1_ rx -- otg_fs_ id -- dcmi_d1 - event out pa11 - tim1_ch4 -- - - - usart1_ cts - can1_rx otg_fs_ dm -- - lcd_r4 event out pa12 - tim1_etr -- - - - usart1_ rts - can1_tx otg_fs_ dp -- - lcd_r5 event out pa13 jtms- swdio ---------- - --- event out pa14 jtck- swclk ---------- - --- event out pa15 jtdi tim2_ch1/ tim2_etr -- -spi1_nss spi3_nss/ i2s3_ws -- - - - - - - event ?out
pinouts and pin description stm32f479xx 74/217 docid028010 rev 3 port b pb0 - tim1_ch2n tim3_ch3 tim8_ch2 n -----lcd_r3 otg_hs _ulpi_d1 eth_mii_ rxd2 - - lcd_g1 event out pb1 - tim1_ch3n tim3_ch4 tim8_ch3 n ----- lcd_r6 otg_hs _ulpi_d2 eth_mii_ rxd3 -- lcd_g0 event out pb2 -- -- - - ----- - - -- event out pb3 jtdo/t races wo tim2_ch2 -- spi1_sck spi3_sck/ i2s3_ck -- - - - - - - event out pb4 njtrst - tim3_ch1 -- spi1_miso spi3_mis o i2s3ext_s d -- - - - - - event out pb5 -- tim3_ch2 - i2c1_smba spi1_mosi spi3_mos i/i2s3_sd - can2_rx otg_hs _ulpi_d7 eth_pps out fmc_ sdcke1 dcmi_d10 lcd_g7 event out pb6 -- tim4_ch1 - i2c1_scl -- usart1_t x - can2_tx quadspi _bk1_nc s - fmc_ sdne1 dcmi_d5 event out pb7 -- tim4_ch2 - i2c1_sda -- usart1_ rx - - -- fmc_nl dcmi_vs ync event out pb8 -- tim4_ch3 tim10_ch 1 i2c1_scl ---- can1_rx - eth_mii_ txd3 sdio_d4 dcmi_d6 lcd_b6 event out pb9 -- tim4_ch4 tim11_ch 1 i2c1_sda spi2_nss/i 2s2_ws --- can1_tx -- sdio_d5 dcmi_d7 lcd_b7 event out pb10 - tim2_ch3 -- i2c2_scl spi2_sck/i 2s2_ck - usart3_t x - quadspi_ bk1_ncs otg_hs _ulpi_d3 eth_mii_rx_ er - - lcd_g4 event out pb11 - tim2_ch4 -- i2c2_sda - usart3_ rx - otg_hs _ulpi_d4 eth_mii_tx_ en/eth_rmii _tx_en - dsihost_ te lcd_g5 event out pb12 - tim1_bkin -- i2c2_smba spi2_nss/i 2s2_ws - usart3_ ck - can2_rx otg_hs _ulpi_d5 eth_mii_txd 0/eth_rmii_t xd0 otg_hs_ id -- event out pb13 - tim1_ch1n -- - spi2_sck/i 2s2_ck - usart3_ cts - can2_tx otg_hs _ulpi_d6 eth_mii_txd 1/eth_rmii_t xd1 --- event out pb14 - tim1_ch2n - tim8_ch2 n - spi2_miso i2s2ext_s d usart3_ rts - tim12_ch1 -- otg_hs_ ?dm -- event out pb15 rtc_re fin tim1_ch3n - tim8_ch3 n - spi2_mosi /i2s2_sd --- tim12_ch2 -- otg_hs_ dp -- event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
stm32f479xx pinouts and pin description docid028010 rev 3 75/217 port c pc0 - - - - - - - - - - otg_hs _ulpi_st p - fmc_sdn we - lcd_r5 event out pc1 traced 0 ---- spi2_mosi /i2s2_sd sai1_sd_ a -- - eth_mdc --- event out pc2 -- - - - spi2_miso i2s2ext_s d -- - otg_hs _ulpi_di r eth_mii_txd 2 fmc_sdn e0 -- event out pc3 -- - - - spi2_mosi /i2s2_sd ---- otg_hs _ulpi_n xt eth_mii_tx_ clk fmc_sdc ke0 -- event out pc4 -- -- - - ----- eth_mii_rxd 0/eth_rmii_r xd0 fmc_sdn e0 -- event out pc5 -- -- - - ----- eth_mii_rxd 1/eth_rmii_r xd1 fmc_sdc ke0 -- event out pc6 -- tim3_ch1 tim8_ch1 - i2s2_mck -- usart6 _tx -- - sdio_d6 dcmi_d0 lcd_hsy nc event out pc7 -- tim3_ch2 tim8_ch2 -- i2s3_mck - usart6 _rx -- - sdio_d7 dcmi_d1 lcd_g6 event out pc8 traced 1 - tim3_ch3 tim8_ch3 ---- usart6 _ck -- - sdio_d0 dcmi_d2 - event out pc9 mco2 - tim3_ch4 tim8_ch4 i2c3_sda i2s_ckin --- quadspi_ bk1_io0 -- sdio_d1 dcmi_d3 - event out pc10 - ----- spi3_sck/ i2s3_ck usart3_ tx uart4_ tx quadspi_ bk1_io1 -- sdio_d2 dcmi_d8 lcd_r2 event out pc11 - ---- i2s3ext_sd spi3_mis o usart3_ rx uart4_ rx quadspi_ bk2_ncs -- sdio_d3 dcmi_d4 - event out pc12 traced 3 ---- - spi3_mos i/i2s3_sd usart3_ ck uart5_ tx -- - sdio_ck dcmi_d9 - event out pc13 -- -- - - ----- - - -- event out pc14 -- -- - - ----- - - -- event out pc15 -- -- - - ----- - - -- event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
pinouts and pin description stm32f479xx 76/217 docid028010 rev 3 port d pd0 - - - - - - - - - can1_rx - - fmc_d2 - - event out pd1 -- -- - - --- can1_tx -- fmc_d3 -- event out pd2 traced 2 - tim3_etr -- --- uart5_ rx -- - sdio_cmd dcmi_d11 - event out pd3 -- - - - spi2_sck/i 2s2_ck - usart2_ cts -- - - fmc_clk dcmi_d5 lcd_g7 event out pd4 -- - - - - - usart2_ rts -- - - fmc_noe -- event out pd5 -- - - - - - usart2_t x -- - - fmc_nwe -- event out pd6 -- - - - spi3_mosi /i2s3_sd sai1_sd_ a usart2_ rx -- - - fmc_nwai t dcmi_d10 lcd_b2 event out pd7 -- - - - - - usart2_ ck -- - - fmc_ne1 -- event out pd8 -- - - - - - usart3_t x -- - - fmc_d13 -- event out pd9 -- - - - - - usart3_ rx -- - - fmc_d14 -- event out pd10 -- - - - - - usart3_ ck -- - - fmc_d15 - lcd_b3 event out pd11 -- - - - - - usart3_ cts - quadspi_ bk1_io0 -- fmc_a16/f mc_cle -- event out pd12 -- tim4_ch1 -- -- usart3_ rts - quadspi_ bk1_io1 -- fmc_a17/f mc_ale -- event out pd13 -- tim4_ch2 -- ---- quadspi_ bk1_io3 -- fmc_a18 -- event out pd14 -- tim4_ch3 -- ---- - -- fmc_d0 -- event out pd15 -- tim4_ch4 -- ---- - -- fmc_d1 -- event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
stm32f479xx pinouts and pin description docid028010 rev 3 77/217 port e pe0 - - tim4_etr - - - - - uart8_ rx - - - fmc_nbl0 dcmi_d2 - event out pe1 -- -- - - -- uart8_ tx -- - fmc_nbl1 dcmi_d3 - event out pe2 tracec lk ---- spi4_sck sai1_mcl k_a -- quadspi_ bk1_io2 - eth_mii_txd 3 fmc_a23 -- event out pe3 traced 0 ---- - sai1_sd_ b -- - - - fmc_a19 -- event out pe4 traced 1 ---- spi4_nss sai1_fs_ a -- - - - fmc_a20 dcmi_d4 lcd_b0 event out pe5 traced 2 -- tim9_ch1 - spi4_miso sai1_sck _a -- - - - fmc_a21 dcmi_d6 lcd_g0 event out pe6 traced 3 -- tim9_ch2 - spi4_mosi sai1_sd_ a -- - - - fmc_a22 dcmi_d7 lcd_g1 event out pe7 - tim1_etr -- - - -- uart7_ rx - quadspi _bk2_io0 - fmc_d4 -- event out pe8 - tim1_ch1n -- - - -- uart7_ tx - quadspi _bk2_io1 - fmc_d5 -- event out pe9 - tim1_ch1 -- - - ---- quadspi _bk2_io2 - fmc_d6 -- event out pe10 - tim1_ch2n -- - - ---- quadspi _bk2_io3 - fmc_d7 -- event out pe11 - tim1_ch2 -- - spi4_nss ----- - fmc_d8 - lcd_g3 event out pe12 - tim1_ch3n -- - spi4_sck ----- - fmc_d9 - lcd_b4 event out pe13 - tim1_ch3 -- - spi4_miso ----- - fmc_d10 - lcd_de event out pe14 - tim1_ch4 -- - spi4_mosi ----- - fmc_d11 - lcd_clk event out pe15 - tim1_bkin -- - - ----- - fmc_d12 - lcd_r7 event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
pinouts and pin description stm32f479xx 78/217 docid028010 rev 3 port f pf0 - - - - i2c2_sda - - - - - - - fmc_a0 - - event out pf1 - - - - i2c2_scl - - - - - - - fmc_a1 - - event out pf2 - - - - i2c2_smba - - - - - - - fmc_a2 - - event out pf3 - - - - - - - - - - - - fmc_a3 - - event out pf4 - - - - - - - - - - - - fmc_a4 - - event out pf5 - - - - - - - - - - - - fmc_a5 - - event out pf6 - - - tim10_ch 1 -spi5_nss sai1_ sd_b - uart7_ rx quadspi_ bk1_io3 -- --- event out pf7 - - - tim11_ch 1 - spi5_sck sai1_ mclk_b - uart7_ tx quadspi_ bk1_io2 -- --- event out pf8 - - - - - spi5_miso sai1_ sck_b - - tim13_ch1 quadspi _bk1_io0 ---- event out pf9 - - - - - spi5_mosi sai1_ fs_b - - tim14_ch1 quadspi _bk1_io1 ---- event out pf10 - - - - - - - - - quadspi_ clk - - dcmi_d11 lcd_de event out pf11 - - - - - spi5_mosi - - - - - - fmc_sdn ras dcmi_d12 - event out pf12-- -- - - ----- -fmc_a6-- event out pf13-- -- - - ----- -fmc_a7-- event out pf14-- -- - - ----- -fmc_a8-- event out pf15-- -- - - ----- -fmc_a9-- event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
stm32f479xx pinouts and pin description docid028010 rev 3 79/217 port g pg0 - - - - - - - - - - - - fmc_a10 - - event out pg1 - - - - - - - - - - - - fmc_a11 -- event out pg2 - - - - - - - - - - - - fmc_a12 -- event out pg3 - - - - - - - - - - - - fmc_a13 -- event out pg4 - - - - - - - - - - - - fmc_a14/f mc_ba0 -- event out pg5 - - - - - - - - - - - - fmc_a15/f mc_ba1 -- event out pg6 - - - - - - - - - - - - dcmi_d12 lcd_r7 event out pg7 - - - - - sai1_mcl k_a usart6 _ck - - - fmc_int dcmi_d13 lcd_clk event out pg8 - - - - - spi6_nss - - usart6 _rts -- eth_pps_ou t fmc_sdcl k lcd_g7 event out pg9 - - - - - - - - usart6 _rx quadspi_ bk2_io2 -- fmc_ne2/ fmc_nce dcmi_vs ync event out pg1 0 - - - - - - - - lcd_g3 - - fmc_ne3 dcmi_d2 lcd_b2 event out pg11 - - - - - - - - - - - eth_mii_tx_ en/eth_rmii _tx_en - dcmi_d3 lcd_b3 event out pg1 2 - - - - - spi6_miso - - usart6 _rts lcd_b4 - - fmc_ne4 - lcd_b1 event out pg1 3 traced 0 ----spi6_sck-- usart6 _cts -- eth_mii_txd 0/eth_rmii_t xd0 fmc_a24 - lcd_r0 event out pg1 4 traced 1 - - - - spi6_mosi - - usart6 _tx quadspi_ bk2_io3 - - fmc_a25 - lcd_b0 event out pg1 5 -- - - - - - - usart6 _cts -- - fmc_ sdncas dcmi_d13 - event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
pinouts and pin description stm32f479xx 80/217 docid028010 rev 3 port h ph0 - - - - - - - - - - - - - - - event out ph1 - - - - - - - - - - - - - - event out ph2 - - - - - - - - - quadspi_ bk2_io0 - eth_mii_crs fmc_sdc ke0 - lcd_r0 event out ph3 - - - - - - - - - quadspi_ bk2_io1 - eth_mii_col fmc_sdn e0 - lcd_r1 event out ph4 - - - - i2c2_scl - - - - lcd_g5 otg_hs _ulpi_n xt - - - lcd_g4 event out ph5 - - - - i2c2_sda spi5_nss - - - - - - fmc_sdn we -- event out ph6 - - - - i2c2_smba spi5_sck - - - tim12_ch1 - eth_mii_rxd 2 fmc_sdn e1 -- event out ph7 - - - - i2c3_scl spi5_miso - - - - - eth_mii_rxd 3 fmc_sdc ke1 dcmi_d9 - event out ph8 - - - - i2c3_sda - - - - - - - fmc_d16 dcmi_hs ync lcd_r2 event out ph9 - - - - i2c3_smba - - - - tim12_ch2 - - fmc_d17 dcmi_d0 lcd_r3 event out ph10 - - tim5_ch1 - - - - - - - - - fmc_d18 dcmi_d1 lcd_r4 event out ph11 - - tim5_ch2 - - - - - - - - - fmc_d19 dcmi_d2 lcd_r5 event out ph12 - - tim5_ch3 - - - - - - - - - fmc_d20 dcmi_d3 lcd_r6 event out ph13 - - - tim8_ch1 n - - - - - can1_tx - - fmc_d21 - lcd_g2 event out ph14 - - - tim8_ch2 n - - - - - - - - fmc_d22 dcmi_d4 lcd_g3 event out ph15 - - - tim8_ch3 n - - - - - - - - fmc_d23 dcmi_d11 lcd_g4 event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
stm32f479xx pinouts and pin description docid028010 rev 3 81/217 port i pi0 - - tim5_ch4 - - spi2_nss/i 2s2_ws - - - - - - fmc_d24 dcmi_d13 lcd_g5 event out pi1 - - - - - spi2_sck/i 2s2_ck - - - - - - fmc_d25 dcmi_d8 lcd_g6 event out pi2 - - - tim8_ch4 - spi2_miso i2s2ext_s d - - - - - fmc_d26 dcmi_d9 lcd_g7 event out pi3 - - - tim8_etr - spi2_mosi /i2s2_sd - - - - - - fmc_d27 dcmi_d10 event out pi4 - - - tim8_bki n - - - - - - - - fmc_nbl2 dcmi_d5 lcd_b4 event out pi5 - - - tim8_ch1 - - - - - - - - fmc_nbl3 dcmi_vs ync lcd_b5 event out pi6 - - - tim8_ch2 - - - - - - - - fmc_d28 dcmi_d6 lcd_b6 event out pi7 - - - tim8_ch3 - - - - - - - - fmc_d29 dcmi_d7 lcd_b7 event out pi8 - - - - - - - - - - - - - - event out pi9 - - - - - - - - - can1_rx - - fmc_d30 - lcd_vsy nc event out pi10 - - - - - - - - - - - eth_mii_rx_ er fmc_d31 - lcd_hsy nc event out pi11 - - - - - - - - - lcd_g6 otg_hs _ulpi _dir ---- event out pi12 - - - - - - - - - - - - - - lcd_hsy nc event out pi13 - - - - - - - - - - - - - - lcd_vsy nc event out pi14 - - - - - - - - - - - - - - lcd_clk event out pi15 - - - - - - - - - lcd_g2 - - - - lcd_r0 event ?out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
pinouts and pin description stm32f479xx 82/217 docid028010 rev 3 port j pj0 - - - - - - - - - lcd_r7 - - - - lcd_r1 event out pj1 - - - - - - - - - - - - - - lcd_r2 event out pj2 - - - - - - - - - - - - - dsihost _te lcd_r3 event out pj3 - - - - - - - - - - - - - - lcd_r4 event out pj4 - - - - - - - - - - - - - - lcd_r5 event out pj5 - - - - - - - - - - - - - - lcd_r6 event out pj12 - - - - - - - - - lcd_g3 - - - - lcd_b0 event out pj13 - - - - - - - - - lcd_g4 - - - - lcd_b1 event out pj14 - - - - - - - - - - - - - - lcd_b2 event out pj15 - - - - - - - - - - - - - - lcd_b3 event out port k pk3 - - - - - - - - - - - - - - lcd_b4 event out pk4 - - - - - - - - - - - - - - lcd_b5 event out pk5 - - - - - - - - - - - - - - lcd_b6 event out pk6 - - - - - - - - - - - - - - lcd_b7 event out pk7 - - - - - - - - - - - - - - lcd_de event out table 12. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/ 5 tim8/9/ 10/11 i2c1/2/3 spi1/2/3 /4/5/6 spi2/3/ sai1 spi2/3/ usart 1/2/3 usar t6/ uart 4/5/7/ 8 can1/2/ tim12/ 13/14/ quad spi/lcd quad spi/ot g2_hs /otg1 _fs eth fmc/ sdio/ otg2_ fs dcmi/ dsi host lcd sys
docid028010 rev 3 83/217 stm32f479xx memory mapping 87 4 memory mapping the memory map is shown in figure 21 . figure 21. memory map 06y9 0e\wh %orfn &ruwh[ ? ,qwhuqdo shulskhudov 0e\wh %orfn )0& [ [))))))) [ [))))))) [ [))))))) [ [))))))) [ [))))))) [$ [&))))))) [' ['))))))) [( [)))))))) 5hvhuyhg [[))) [[)))) [[))))))) [ 5hvhuyhg [))) [[)))) [ 5hvhuyhg [&[))))))) $+% [['))))))) $+% [%)) [ 65$0 .%doldvhge\elwedqglqj [[)))) $3% $3% [)) [[)))) 5hvhuyhg [[))))))) [)))) $+% 5hvhuyhg )odvkphpru\ [[))))))) [)))[)))$) [)))&[)))& ) [[))))) [[)))))) [[))))) 6\vwhpphpru\ 5hvhuyhg 5hvhuyhg $oldvhgwr)odvkv\vwhp phpru\ru65$0ghshqglqj rqwkh%227slqv [)))&[))))))) [)))$[)))))) &&0gdwd5$0 .%gdwd65$0 [[)))) [[))(%))) [))(&[))(& ) 2swlrqe\whv 5hvhuyhg [))(&[))()))) [ &ruwh[ ? 0 lqwhuqdoshulskhudo [([())))) 5hvhuyhg [([)))))))) 0e\wh %orfn )0&dqg 48$'63, 0e\wh %orfn )0&edqndqg 48$'63,edqn 0e\wh %orfn )0&edqnwr 48$'63,edqn 0e\wh %orfn 3hulskhudov 0e\wh %orfn 65$0 0e\wh %orfn 65$0 65$0 .%doldvhge\elwedqglqj 65$0 .%doldvhge\elwedqglqj 5hvhuyhg 2swlrq%\whv 5hvhuyhg 5hvhuyhg
memory mapping stm32f479xx 84/217 docid028010 rev 3 table 13. stm32f479xx register boundary addresses (1) bus boundary address peripheral - 0xe00f ffff - 0xffff ffff reserved cortex ? -m4 0xe000 0000 - 0xe00f ffff cortex ? -m4 internal peripherals ahb3 0xd000 0000 - 0xdfff ffff fmc bank 6 0xc000 0000 - 0xcfff ffff fmc bank 5 0xa000 1000 - 0xa0001fff q uad-spi control register 0xa000 2000 - 0xbfff ffff reserved 0xa000 0000- 0xa000 0fff fmc control register 0x9000 0000 - 0x9fff ffff quad-spi bank 0x8000 0000 - 0x8fff ffff fmc bank 3 0x7000 0000 - 0x7fff ffff fmc bank 2 (reserved) 0x6000 0000 - 0x6fff ffff fmc bank 1 - 0x5006 0c00- 0x5fff ffff reserved ahb2 0x5006 0800 - 0x5006 0bff rng 0x5006 0400 - 0x5006 07ff hash 0x5006 0000 - 0x5006 03ff cryp 0x5005 0400 - 0x5005 ffff reserved 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000- 0x5004 ffff reserved 0x5000 0000 - 0x5003 ffff usb otg fs
docid028010 rev 3 85/217 stm32f479xx memory mapping 87 - 0x4008 0000- 0x4fff ffff reserved ahb1 0x4004 0000 - 0x4007 ffff usb otg hs 0x4002 bc00- 0x4003 ffff reserved 0x4002 b000 - 0x4002 bbff chrom (dma2d) 0x4002 9400 - 0x4002 afff reserved 0x4002 9000 - 0x4002 93ff ethernet mac 0x4002 8c00 - 0x4002 8fff 0x4002 8800 - 0x4002 8bff 0x4002 8400 - 0x4002 87ff 0x4002 8000 - 0x4002 83ff 0x4002 6800 - 0x4002 7fff reserved 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 5fff reserved 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2c00 - 0x4002 2fff reserved 0x4002 2800 - 0x4002 2bff gpiok 0x4002 2400 - 0x4002 27ff gpioj 0x4002 2000 - 0x4002 23ff gpioi 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1800 - 0x4002 1bff gpiog 0x4002 1400 - 0x4002 17ff gpiof 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa table 13. stm32f479xx register boundary addresses (1) (continued) bus boundary address peripheral
memory mapping stm32f479xx 86/217 docid028010 rev 3 apb2 0x4001 7400 - 0x4001 ffff reserved 0x4001 6c00 - 0x4001 73ff dsi host 0x4001 6800 - 0x4001 6bff lcd-tft 0x4001 5c00 - 0x4001 67ff reserved 0x4001 5800 - 0x4001 5bff sai1 0x4001 5400 - 0x4001 57ff spi6 0x4001 5000 - 0x4001 53ff spi5 0x4001 4c00 - 0x4001 4fff reserved 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff spi4 0x4001 3000 - 0x4001 33ff spi1 0x4001 2c00 - 0x4001 2fff sdio 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 table 13. stm32f479xx register boundary addresses (1) (continued) bus boundary address peripheral
docid028010 rev 3 87/217 stm32f479xx memory mapping 87 - 0x4000 8000- 0x4000 ffff reserved apb1 0x4000 7c00 - 0x4000 7fff uart8 0x4000 7800 - 0x4000 7bff uart7 0x4000 7400 - 0x4000 77ff dac 0x4000 7000 - 0x4000 73ff pwr 0x4000 6c00 - 0x4000 6fff reserved 0x4000 6800 - 0x4000 6bff can2 0x4000 6400 - 0x4000 67ff can1 0x4000 6000 - 0x4000 63ff reserved 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 5000 - 0x4000 53ff uart5 0x4000 4c00 - 0x4000 4fff uart4 0x4000 4800 - 0x4000 4bff usart3 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff i2s3ext 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff i2s2ext 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2bff rtc & bkp registers 0x4000 2400 - 0x4000 27ff reserved 0x4000 2000 - 0x4000 23ff tim14 0x4000 1c00 - 0x4000 1fff tim13 0x4000 1800 - 0x4000 1bff tim12 0x4000 1400 - 0x4000 17ff tim7 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 1. the reserved boundary address are shown in grayed cells table 13. stm32f479xx register boundary addresses (1) (continued) bus boundary address peripheral
electrical characteristics stm32f479xx 88/217 docid028010 rev 3 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.7 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 22 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 23 . figure 22. pin loading conditi ons figure 23. pin input voltage -36 #p& -#5pin -36 -#5pin 6 ).
docid028010 rev 3 89/217 stm32f479xx electrical characteristics 190 5.1.6 power supply scheme figure 24. power supply scheme 1. to connect bypass_reg and pdr_on pins, refer to section 2.19 and section 2.20 . 2. the two 2.2 f ceramic capacitors on v cap_1 and v cap_2 should be replaced by two 100 nf decoupling capacitors when the voltage regulator is off. 3. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. 4. v dda and v ssa must be connected to v dd and v ss , respectively. caution: each power supply pair (v dd /v ss , v dda /v ssa ...) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure good operation of the device. it is not recommended to remove filterin g capacitors to reduce pcb size or cost. this might cause incorrect operation of the device. 069 %dfnxsflufxlwu\ 26&.57& :dnhxsorjlf %dfnxsuhjlvwhuv edfnxs5$0 .huqhoorjlf &38gljlwdo 5$0 $qdorj 5&v3// 3rzhu vzlwfk 9 %$7 *3,2v 287 ,1 ?q) ??) 9 %$7 wr9 9rowdjh uhjxodwru 9 ''$ $'& /hyhovkliwhu ,2 /rjlf 9 '' q) ?) )odvkphpru\ 9 &$3b 9 &$3b ??) %<3$66b5(* 3'5b21 5hvhw frqwuroohu 9 '' 9 66 9 '' 9 5() 9 5() 9 66$ 9 5() q) ?) 27*)6 3+< 9 ''86% q) 9 ''86% '6, 3+< '6, 9rowdjh uhjxodwru 9 '''6, 9 &$3'6, 9 '''6, 9 66'6, ?)
electrical characteristics stm32f479xx 90/217 docid028010 rev 3 5.1.7 current consumption measurement figure 25. current consum ption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 14 , table 15 , and table 16 may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extend ed periods may affect device reliability. ai 6 "!4 6 $$ 6 $$! ) $$ ?6 "!4 ) $$ table 14. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd , v ddusb , v dddsi and v bat ) (1) 1. all main power (v dd , v dda , v ddusb , v dddsi ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ? 0.3 4.0 v v in input voltage on ft pins (2) 2. v in maximum value must always be respected. refer to table 15 for the values of the maximum allowed injected current. v ss ? 0.3 v dd +4.0 input voltage on tta pins v ss ? 0.3 4.0 input voltage on any other pin v ss ? 0.3 4.0 input voltage on boot pin v ss 9.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins (3) 3. including v ref- pin -50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.18
docid028010 rev 3 91/217 stm32f479xx electrical characteristics 190 table 15. current characteristics symbol ratings max. unit i vdd total current into sum of all v dd_x power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 290 ma i vss total current out of sum of all v ss_x ground lines (sink) (1) ? 290 i vddusb total current into v ddusb power line (source) 25 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss_x ground line (sink) (1) ? 100 i io output current sunk by any i/o and control pin 25 output current sourced by any i/os and control pin ? 25 i io total output current sunk by sum of all i/o and control pins (2) 2. this current consumption must be correctly distri buted over all i/os and control pins. the total output current must not be sunk/sourced between two consecut ive power supply pins refe rring to high pin count lqfp packages. 120 total output current sunk by sum of all usb i/os 25 total output current sourced by sum of all i/os and control pins (2) ? 120 i inj(pin) (3) 3. negative injection disturbs the analog performance of the device. see note in section 5.3.24 . injected current on ft pins (4) 4. positive injection is not possi ble on these i/os and does not occur for input voltages lower than the specified maximum value. ? 5/+0 injected current on nrst and boot0 pins (4) injected current on tta pins (5) 5. a positive injection is induced by v in >v dda while a negative inje ction is induced by v in electrical characteristics stm32f479xx 92/217 docid028010 rev 3 5.3 operating conditions 5.3.1 general operating conditions table 17. general operating conditions symbol parameter conditions (1) min typ max unit f hclk internal ahb clock frequency power scale 3 (vos[1:0] bits in pwr_cr register = 0x01), regulator on, over-drive off 0-120 mhz power scale 2 (vos[1:0] bits in pwr_cr register = 0x10), regulator on over-drive off 0 -144 over-drive on -168 power scale 1 (vos[1:0] bits in pwr_cr register= 0x11), regulator on over-drive off 0 -168 over-drive on -180 f pclk1 internal apb1 clock frequency over-drive off 0 - 42 over-drive on 0 - 45 f pclk2 internal apb2 clock frequency over-drive off 0 - 84 over-drive on 0 - 90 v dd standard operating voltage - 1.7 (2) -3.6 v v dda (3)(4) analog operating voltage (adc limited to 1.2 m samples) must be the same potential as v dd (5) 1.7 (2) -2.4 analog operating voltage (adc limited to 2.4 m samples) 2.4 - 3.6 v ddusb usb supply voltage (supply voltage for pa11, pa12, pb14 and pb15 pins) usb not used 1.7 3.3 3.6 usb used 3.0 - 3.6 v dddsi dsi system operating voltage - 1.7 (2) -3.6 v bat backup operating voltage - 1.65 - 3.6
docid028010 rev 3 93/217 stm32f479xx electrical characteristics 190 v 12 regulator on: 1.2 v internal voltage on v cap_1 /v cap_2 pins power scale 3 ((vos[1:0] bits in pwr_cr register = 0x01), 120 mhz hclk max frequency 1.08 1.14 1.20 v power scale 2 ((vos[1:0] bits in pwr_cr register = 0x10), 144 mhz hclk max frequency with over-drive off or 168 mhz with over-drive on 1.20 1.26 1.32 power scale 1 ((vos[1:0] bits in pwr_cr register = 0x11), 168 mhz hclk max frequency with over-drive off or 180 mhz with over-drive on 1.26 1.32 1.40 regulator off: 1.2 v external voltage must be supplied from external regulator on v cap_1 /v cap_2 pins (6) max frequency 120 mhz 1.10 1.14 1.20 max frequency 144 mhz 1.20 1.26 1.32 max frequency 168 mhz 1.26 1.32 1.38 v in input voltage on rst and ft pins (7) 2v v dd 3.6 v ? 0.3 - 5.5 v v dd 2v ? 0.3 - 5.2 input voltage on tta pins - ? 0.3 - v dda +0.3 input voltage on boot0 pin - 0 - 9 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (8) lqfp100 - - 465 mw lqfp144 - - 500 wlcsp168 - - 645 ufbga169 - - 385 lqfp176 - - 526 ufbga176 - - 513 lqfp208 - - 1053 tfbga216 - - 690 t a ambient temperature for 6 suffix version maximum power dissipation ? 40 - 85 c low power dissipation (9) ? 40 - 105 ambient temperature for 7 suffix version maximum power dissipation ? 40 - 105 low power dissipation (9) ? 40 - 125 t j junction temperature range 6 suffix version ? 40 - 105 7 suffix version ? 40 - 125 1. the over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 v. 2. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 2.19.2 ). 3. when the adc is used, refer to table 76 . 4. if v ref+ pin is present, it must res pect the following condition: v dda -v ref+ < 1.2 v. 5. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 6. the over-drive mode is not supported when the internal regulator is off. table 17. general operating conditions (continued) symbol parameter conditions (1) min typ max unit
electrical characteristics stm32f479xx 94/217 docid028010 rev 3 5.3.2 vcap1/vcap2 external capacitor stabilization for the main regula tor is achieved by connecting an external capacitor c ext to the vcap1/vcap2 pins. c ext is specified in table 19 . figure 26. external capacitor c ext 1. legend: esr is the equivalent series resistance. 7. to sustain a voltage higher than vdd+0.3, the inter nal pull-up and pull-down re sistors must be disabled 8. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 9. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 18. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum hclk frequency vs. flash memory wait states (1)(2) i/o operation possible flash memory operations v dd = 1.7 to 2.1 v (3) conversion time up to 1.2 msps 20 mhz (4) 168 mhz with 8 wait states and over-drive off no i/o compensation 8-bit erase and program operations only v dd = 2.1 to 2.4 v 22 mhz 180 mhz with 8 wait states and over-drive on 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 180 mhz with 7 wait states and over-drive on i/o compensation works 16-bit erase and program operations v dd = 2.7 to 3.6 v (5) 30 mhz 180 mhz with 5 wait states and over-drive on 32-bit erase and program operations 1. applicable only when the code is executed from flash memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since t he art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 2.19.2 ). 4. prefetch is not available. 5. when v ddusb is connected to v dd , the voltage range for usb full speed phys can drop down to 2.7 v. however the electrical characte ristics of d- and d+ pins will be degraded between 2.7 and 3 v. 069 (65 5 /hdn &
docid028010 rev 3 95/217 stm32f479xx electrical characteristics 190 5.3.3 operating conditi ons at power-up / powe r-down (regulator on) subject to general operating conditions for t a . table 20. operating conditions at power-up / power-down (regulator on) 5.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . 5.3.5 reset and power cont rol block characteristics the parameters given in table 22 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . table 19. vcap1/vcap2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter conditions cext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 table 21. operating conditions at pow er-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20
electrical characteristics stm32f479xx 96/217 docid028010 rev 3 table 22. reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 pls[2:0]=001 (rising edge) 2.23 2.30 2.37 pls[2:0]=001 (falling edge) 2.13 2.19 2.25 pls[2:0]=010 (rising edge) 2.39 2.45 2.51 pls[2:0]=010 (falling edge) 2.29 2.35 2.39 pls[2:0]=011 (rising edge) 2.54 2.60 2.65 pls[2:0]=011 (falling edge) 2.44 2.51 2.56 pls[2:0]=100 (rising edge) 2.70 2.76 2.82 pls[2:0]=100 (falling edge) 2.59 2.66 2.71 pls[2:0]=101 (rising edge) 2.86 2.93 2.99 pls[2:0]=101 (falling edge) 2.65 2.84 2.92 pls[2:0]=110 (rising edge) 2.96 3.03 3.10 pls[2:0]=110 (falling edge) 2.85 2.93 2.99 pls[2:0]=111 (rising edge) 3.07 3.14 3.21 pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v pvdhyst (1) pvd hysteresis - - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 1.68 1.76 v rising edge 1.64 1.72 1.80 v pdrhyst (1) pdr hysteresis - - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 rising edge 2.53 2.59 2.63 v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 rising edge 2.85 2.92 2.97 v borhyst (1) bor hysteresis - - 100 - mv t rsttempo (1)(2) por reset temporization - 0.5 1.5 3.0 ms i rush (1) inrush current on voltage regulator power-on (por or wakeup from standby) - - 160 200 ma e rush (1) inrush energy on voltage regulator power-on (por or wakeup from standby) v dd = 1.7 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. guaranteed by design. 2. the reset temporization is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is read by the user application code.
docid028010 rev 3 97/217 stm32f479xx electrical characteristics 190 5.3.6 over-drive switching characteristics when the over-drive mode switches from enabl ed to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. the over-drive switching c haracteristics are given in table 23 . they are subject to general operating conditions for t a . 5.3.7 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 25 . all the run-mode current consumption measurements given in this section are performed with a reduced code that gives a c onsumption equivalent to coremark ? code. table 23. over-drive switching characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit t od_swen over_drive switch enable time hsi - 45 - s hse max for 4 mhz and min for 26 mhz 45 - 100 external hse 50 mhz - 40 - t od_swdis over_drive switch disable time hsi - 20 - hse max for 4 mhz and min for 26 mhz. 20 - 80 external hse 50 mhz - 15 -
electrical characteristics stm32f479xx 98/217 docid028010 rev 3 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load). ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted both to f hclk frequency and v dd range (see table 18: limitations depending on the operating power supply range ). ? when the regulator is off, the v 12 is provided externally, as described in table 17: general operating conditions . ? the voltage scaling and over-drive mode are adjusted to f hclk frequency as follows: ? scale 3 for f hclk 120 mhz ? scale 2 for 120 mhz < f hclk 144 mhz ? scale 1 for 144 mhz < f hclk 180 mhz. the over-drive is only on at 180 mhz. ? the system clock is hclk, f pclk1 = f hclk /4, and f pclk2 = f hclk /2. ? external clock frequency is 25 mhz and pll is on when f hclk is higher than 25 mhz. ? the typical current consumption values are obtained for 1.7 v v dd 3.6 v voltage range and for ambient temperature t a = 25 c unless otherwise specified. ? the maximum values are obtained for 1.7 v v dd 3.6 v voltage range and a maximum ambient temperature (t a ), unless otherwise specified. ? for the voltage range 1.7 v v dd 2.1 v the maximum frequency is 168 mhz.
docid028010 rev 3 99/217 stm32f479xx electrical characteristics 190 table 24. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram, regulator on symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode all peripherals enabled (2)(3) 180 103 109 (4) 142 175 (4) ma 168 94 99 124 149 150 84 89 114 140 144 77 81 104 127 120 57 60 79 98 90 43 46 64 84 60 30 33 51 70 30 16 19 37 57 25 14 16 34 54 16 7 10 28 48 8472646 4362444 2352343 all peripherals disabled (2) 180 50 56 (4) 89 124 (4) 168 45 51 75 102 150 41 46 70 97 144 37 42 63 88 120 28 31 49 69 90 21 24 42 63 60 15 17 36 56 30 9 11 29 49 25 7 10 28 48 16 4 7 25 45 8362244 4352343 2252343 1. guaranteed based on test during characterization. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma per adc for the analog part. 4. guaranteed by test in production.
electrical characteristics stm32f479xx 100/217 docid028010 rev 3 table 25. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator disabled), regulator on symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode all peripherals enabled (2)(3) 168 97 102 128 154 ma 150 87 92 118 143 144 80 84 108 131 120 65 68 88 108 90 51 54 73 93 60 37 41 59 79 30 21 23 42 62 25 18 20 39 59 all peripherals disabled 168 49 55 79 105 150 44 49 44 100 144 40 45 68 92 120 36 39 58 78 90 29 32 51 71 60 22 25 44 64 30 13 15 34 54 25 11 13 32 52 1. guaranteed based on test during characterization. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma per adc for the analog part.
docid028010 rev 3 101/217 stm32f479xx electrical characteristics 190 table 26. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch), regulator off symbol parameter conditions f hclk (mhz) typ max (1) unit i dd12 i dd t a = 25 c t a = 85 c t a = 105 c i dd12 i dd i dd12 i dd i dd12 i dd i dd12 / i dd supply current in run mode from v 12 and v dd supply all peripherals enabled (2) (3) 168 93 1 98 1 123 1 148 1 ma 150 83 1 88 1 113 1 138 1 144 76 1 80 1 103 1 126 1 120561591781971 90431451641831 60291321501701 30151181361561 25131151341531 all peripherals disabled 168441501721941 150401451681901 144361401621821 120271301481661 90201231411601 60141161351531 30 8 1101281471 25 7 1 9 1271461 1. guaranteed based on test during characterization. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, dsi regulator, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma per adc for the analog part.
electrical characteristics stm32f479xx 102/217 docid028010 rev 3 table 27. typical and maximum current consumption in sleep mode, regulator on symbol parameter conditions f hclk (mhz) typ max (1)(2)(3) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode all peripherals enabled 180 78 88 (4) 118 151 (4) ma 168 71 76 101 127 150 64 71 94 119 144 58 62 85 109 120 43 46 65 85 90 33 37 54 74 60 23 25 44 63 30 13 15 34 53 25 11 13 32 52 16 5 8 27 47 847 25 45 435 24 44 225 23 43 all peripherals disabled 180 23 29 (4) 63 96 (4) 168 21 25 50 76 150 19 23 48 74 144 17 31 43 67 120 13 16 34 54 90 10 13 31 51 60 7 10 28 48 30 5 7 25 45 25 4 7 25 45 16 2 5 23 43 825 23 43 425 23 43 224 23 42 1. guaranteed based on test during characterization. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma per adc for the analog part. 4. guaranteed by test in production.
docid028010 rev 3 103/217 stm32f479xx electrical characteristics 190 table 28. typical and maximum current c onsumption in sleep mode, regulator off symbol parameter conditions f hclk (mhz) typ max (1) unit i dd12 i dd t a = 25 c t a = 85 c t a = 105 c i dd12 i dd i dd12 i dd i dd12 i dd i dd12 / i dd supply current in run mode from v 12 and v dd supply all peripherals enabled 168 70 1 75 1 100 1 126 1 ma 150 63 1 70 1 93 1 118 1 144 57 1 61 1 84 1 108 1 120421451641841 90321361531731 60221241431631 30121141331531 25101121311511 all peripherals disabled 168201241491751 150181221471731 144161191421661 120121141331531 90101121301501 60 7 1 9 1271471 30 4 1 6 1241441 25 4 1 6 1241441 1. guaranteed based on test during characterization.
electrical characteristics stm32f479xx 104/217 docid028010 rev 3 table 29. typical and maximum current consumption in stop mode symbol parameter conditions typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd_stop_nm (normal mode) supply current in stop mode with voltage regulator in main regulator mode flash memory in stop mode, all oscillators off, no independent watchdog 0.63 3 17 33 ma flash memory in deep power down mode, all oscillators off, no independent watchdog 0.58 3 17 33 supply current in stop mode with voltage regulator in low power regulator mode flash memory in stop mode, all oscillators off, no independent watchdog 0.50 2 15 28 flash memory in deep power down mode, all oscillators off, no independent watchdog 0.44 2 15 28 i dd_stop_udm (under-drive mode) supply current in stop mode with voltage regulator in main regulator and under- drive mode flash memory in deep power down mode, main regulator in under-drive mode, all oscillators off, no independent watchdog 0.21 1 6 12 supply current in stop mode with voltage regulator in low power regulator and under- drive mode flash memory in deep power down mode, low power regulator in under-drive mode, all oscillators off, no independent watchdog 0.14 1 6 13 1. data based on characteriza tion, tested in production.
docid028010 rev 3 105/217 stm32f479xx electrical characteristics 190 table 30. typical and maximum current consumption in standby mode symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c v dd = 1.7 v v dd = 2.4 v v dd = 3.3 v v dd = 3.3 v i dd_stby supply current in standby mode backup sram on, rtc and lse oscillator off 1.7 2.5 2.9 6 (3) 18 35 (3) a backup sram off, rtc and lse oscillator off 1.0 1.8 2.20 5 (3) 15 30 (3) backup sram off, rtc on and lse oscillator in power drive mode 1.7 2.7 3.2 7 20 39 backup sram on, rtc on and lse oscillator in power drive mode 2.4 3.4 4.0 8 25 48 backup sram on, rtc on and lse oscillator in high drive mode 3.2 4.2 4.8 10 29 57 backup sram off, rtc on and lse oscillator in high drive mode 2.5 3.5 4.1 8 25 48 1. pdr is off for v dd =1.7 v. when the pdr is off (internal reset off) , the typical current consumption is reduced by additional 1.2 a 2. based on characterization, not tested in production unless otherwise specified. 3. based on characterization, tested in production.
electrical characteristics stm32f479xx 106/217 docid028010 rev 3 figure 27. typical v bat current consumption (rtc on / backup sram on and lse in low drive mode) table 31. typical and maximum current consumption in v bat mode symbol parameter conditions (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c v bat = 1.7 v v bat = 2.4 v v bat = 3.3 v v bat = 3.3 v i dd_vbat backup domain supply current backup sram on, rtc on and lse oscillator in low power mode 1.431 1.577 1.825 1.9 12.0 24.0 a backup sram off, rtc on and lse oscillator in low power mode 0.720 0.849 1.060 1.1 7.0 13.9 backup sram on, rtc on and lse oscillator in high drive mode 2.212 2.368 2.630 2.80 17.3 34.6 backup sram off, rtc on and lse oscillator in high drive mode 1.499 1.637 1.862 2.0 12.3 24.5 backup sram on, rtc and lse off 0.710 0.720 0.760 0.8 (3) 5.0 10.0 (3) backup sram off, rtc and lse off 0.018 0.020 0.024 0.2 (3) 2.0 4.0 (3) 1. crystal used: abracon abs07-120-32.768 khz-t with a c l of 6 pf for typical values. 2. based on characterization, tested in production. 3. based on test during characterization. 0 1 2 3 4 5 6 0 20406080100 i dd_vbat (a) temperature (c) 1.65v 1.70v 1.80v 2.00v 2.40v 2.70v 3.00v 3.30v 3.60v
docid028010 rev 3 107/217 stm32f479xx electrical characteristics 190 figure 28. typical v bat current consumption (rtc on / backup sram on and lse in high drive mode) i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 58: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 33 ), the i/os used by an application also contribute to the current co nsumption. when an i/o pin switches, it uses 0 1 2 3 4 5 6 7 0 20406080100 i dd_vbat (a) temperature (c) 1.65v 1.70v 1.80v 2.00v 2.40v 2.70v 3.00v 3.30v 3.60v
electrical characteristics stm32f479xx 108/217 docid028010 rev 3 the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. table 32. switching output i/o current consumption (1) symbol parameter conditions i/o toggling frequency (fsw) typ unit i ddio i/o switching current v dd = 3.3 v c= c int (2) 2 mhz 0.0 ma 8 mhz 0.2 25 mhz 0.6 50 mhz 1.1 60 mhz 1.3 84 mhz 1.8 90 mhz 1.9 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.1 8 mhz 0.4 25 mhz 1.23 50 mhz 2.43 60 mhz 2.93 84 mhz 3.86 90 mhz 4.07 i sw v dd f sw c =
docid028010 rev 3 109/217 stm32f479xx electrical characteristics 190 on-chip peripheral current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are in analog input configuration. ? all peripherals are disabled unless otherwise mentioned. ? i/o compensation cell enabled. ? the art accelerator is on. ? scale 1 mode selected, internal digital voltage v12 = 1.32 v. ? hclk is the system clock. f pclk1 = f hclk /4, and f pclk2 = f hclk /2. the given value is calculated by measur ing the difference of current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ?f hclk = 180 mhz (scale1 + over-drive on), f hclk = 144 mhz (scale 2), f hclk = 120 mhz (scale 3) ? ambient operating temperature is 25 c and v dd =3.3 v. i ddio i/o switching current v dd = 3.3 v c ext = 10 pf c = c int + c ext + c s 2 mhz 0.18 ma 8 mhz 0.67 25 mhz 2.09 50 mhz 3.6 60 mhz 4.5 84 mhz 7.8 90 mhz 9.8 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.26 8 mhz 1.01 25 mhz 3.14 50 mhz 6.39 60 mhz 10.68 v dd = 3.3 v c ext = 33 pf c = c int + cext + c s 2 mhz 0.33 8 mhz 1.29 25 mhz 4.23 50 mhz 11.02 1. c s is the pcb board capacitance including the pad pin. c s = 7 pf (estimated value). 2. this test is performed by cutting the lqfp176 package pin (pad removal). table 32. switching output i/o current consumption (1) (continued) symbol parameter conditions i/o toggling frequency (fsw) typ unit
electrical characteristics stm32f479xx 110/217 docid028010 rev 3 table 33. peripheral current consumption peripheral i dd (typ) (1) unit scale 1 scale 2 scale 3 ahb1 (up to 180 mhz) gpioa 3.16 3.00 2.58 a/mhz gpiob 2.67 2.62 2.25 gpioc 2.42 2.31 2.10 gpiod 2.22 2.10 1.79 gpioe 2.60 2.48 2.23 gpiof 2.39 2.27 2.08 gpiog 2.27 2.13 1.98 gpioh 2.34 2.20 2.02 gpioi 2.52 2.37 2.17 gpioj 2.16 2.03 1.86 gpiok 2.20 2.06 1.89 otg_hs+ulpi 36.49 33.89 29.90 crc 0.62 0.55 0.50 bkpsram 0.83 0.74 0.63 dma1 (2) 3.3 x n + 6.8 3 x n + 6.3 2.7 x n + 5.5 dma2 (2) 3.4 x n + 5.7 3.1 x n + 5.3 2.8 x n + 4.6 dma2d 33.33 30.66 26.98 eth_mac eth_mac_tx eth_mac_rx eth_mac_ptp 22.30 20.69 18.19 ahb2 (up to 180 mhz) usb_otg_fs 34.33 31.96 28.35 a/mhz dvcmi 3.61 3.35 2.98 rng 1.94 1.82 1.61 cryp 2.42 2.24 2.00 hash 4.14 3.80 3.35 ahb3 (up to 180 mhz) quadspi 16.83 15.57 13.83 a/mhz fmc 17.22 15.92 14.00 bus matrix (3) 12.17 11.19 9.97 a/mhz
docid028010 rev 3 111/217 stm32f479xx electrical characteristics 190 apb1 (up to 45 mhz) tim2 19.11 17.56 15.33 a/mhz tim3 15.62 14.22 12.17 tim4 16.22 14.64 12.83 tim5 18.44 16.72 14.00 tim6 3.18 2.69 2.17 tim7 3.11 2.56 2.00 tim12 8.67 7.56 6.50 tim13 6.11 5.33 4.43 tim14 6.44 5.61 4.67 pwr 17.44 15.61 13.53 usart2 5.44 4.64 3.93 usart3 5.51 4.72 4.00 uart4 5.22 4.64 3.83 uart5 5.33 4.64 3.83 uart7 5.56 4.78 4.10 uart8 5.24 4.64 3.93 i2c1 4.78 4.08 3.43 i2c2 5.11 4.50 3.73 i2c3 4.78 4.08 3.43 spi2/i2s2 (4) 4.11 3.53 3.00 spi3/i2s3 (4) 4.33 3.67 3.17 can1 8.89 7.83 6.87 can2 7.22 6.44 5.50 dac (5) 2.89 2.69 2.40 wwdg 1.73 1.44 1.00 table 33. peripheral current consumption (continued) peripheral i dd (typ) (1) unit scale 1 scale 2 scale 3
electrical characteristics stm32f479xx 112/217 docid028010 rev 3 apb2 (up to 90 mhz) sdio 7.94 7.18 6.37 a/mhz tim1 19.44 17.81 15.80 tim8 19.44 17.81 15.80 tim9 8.44 7.60 6.77 tim10 5.67 5.03 4.50 tim11 5.72 5.10 4.55 adc1 (6) 5.06 4.54 4.05 adc2 (6) 5.00 4.47 3.97 adc3 (6) 5.26 4.75 4.17 usart1 4.83 4.33 3.83 usart6 4.83 4.33 3.83 spi1 2.11 1.76 1.60 spi4 2.11 1.69 1.60 spi5 2.11 1.76 1.60 spi6 2.11 1.76 1.60 syscfg 1.72 1.35 1.22 ltdc 37.61 34.53 30.60 sai1 3.44 3.01 2.72 dsi 32.98 30.32 26.87 1. when the i/o compensation cell is on, i dd typical value increases by 0.22 ma. 2. dma1/dma2 current consumption is calculated by the equation. n: is the number of streams enabled, n= [1..8] 3. the busmatrix is automatically active when at least one master is on. 4. to enable an i2s peripheral, first set the i2smod bit and then the i2se bit in the spi_i2scfgr register. 5. when the dac is on and en1/2 bits are set in da c_cr register, add an additional power consumption of 0.8 ma per dac channel for the analog part. 6. when the adc is on (adon bit set in the adc_cr 2 register), add an additional power consumption of 1.6 ma per adc for the analog part. table 33. peripheral current consumption (continued) peripheral i dd (typ) (1) unit scale 1 scale 2 scale 3
docid028010 rev 3 113/217 stm32f479xx electrical characteristics 190 5.3.8 wakeup time from low-power modes the wakeup times given in table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep modes: the wakeup event is wfe. ? wkup (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd =3.3 v. table 34. low-power mode wakeup timings symbol parameter conditions typ (1) max (1) unit t wusleep (2) wakeup from sleep - 5 6 cpu clock cycles t wustop (2) wakeup from stop mode with mr/lp regulator in normal mode main regulator is on 12.9 13.0 s main regulator is on and flash memory in deep power down mode 105 109 low power regulator is on 22 25.4 low power regulator is on and flash memory in deep power down mode 114 121 t wustop (2) wakeup from stop mode with mr/lp regulator in under-drive mode main regulator in under-drive mode (flash memory in deep power-down mode) 107 111 low power regulator in under-drive mode (flash memory in deep power-down mode) 115 121 t wustdby (2)(3) wakeup from standby mode - 318 371 1. based on test during characterization. 2. the wakeup times are measured from the wakeup event to the point in which the application code reads the first 3. t wustdby maximum value is given at ?40 c.
electrical characteristics stm32f479xx 114/217 docid028010 rev 3 5.3.9 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 58 . however, the recommended clock input waveform is shown in figure 29 . the characteristics given in table 35 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 17 . low-speed external user clock generated from an external source in bypass mode the lse oscillato r is switched off and the inpu t pin is a standard i/o. the external clock signal has to respect the table 58: i/o static characteristics . however, the recommended clock input waveform is shown in figure 30 . the characteristics given in table 36 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 17 . table 35. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) - 1-50mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) --5-pf ducy (hse) duty cycle - 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 36. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50
docid028010 rev 3 115/217 stm32f479xx electrical characteristics 190 figure 29. high-speed external clock source ac timing diagram figure 30. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 37 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization c in(lse) osc32_in input capacitance (1) --5-pf ducy (lse) duty cycle - 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design. table 36. low-speed external user clock characteristics (continued) symbol parameter conditions min typ max unit ai /3 # ?) . %xternal 34-& clocksource 6 (3%( t f(3% t 7(3% ) , 4 (3% t t r(3% t 7(3% f (3%?ext 6 (3%, dl 2 6&b,1 ([whuqdo 670) forfnvrxufh 9 /6(+ w i/6( w :/6( , / 7 /6( w w u/6( w :/6( i /6(bh[w 9 /6(/
electrical characteristics stm32f479xx 116/217 docid028010 rev 3 time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 31 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from www.st.com . figure 31. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. table 37. hse 4-26 mhz oscillator characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit f osc_in oscillator frequency - 4 - 26 mhz r f feedback resistor - - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf@25 mhz - 450 - a v dd =3.3 v, esr= 30 ? , c l =10 pf@25 mhz - 530 - acc hse (2) 2. this parameter depends on the crystal used in the application. the minimum and maximum values must be respected to comply with usb standard specifications. hse accuracy - ? 500 - 500 ppm g m _crit_max maximum critical crystal g m startup - - 1 ma/v t su(hse) (3) 3. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is based on char acterization and not tested in production. it is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms dl 26&b28 7 26&b,1 i +6( & / 5 ) 670) 0+] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq 5 (;7 & /
docid028010 rev 3 117/217 stm32f479xx electrical characteristics 190 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e informations given in th is paragraph are based on characterization results obtained with typical external components specified in table 38 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from www.st.com . figure 32. typical applicati on with a 32.768 khz crystal table 38. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design. symbol parameter conditions min typ max unit r f feedback resistor - - 18.4 - m i dd lse current consumption low power mode (2) 2. lse mode cannot be changed ?on the fly? other wise, a glitch can be generated on oscin pin. --1 a high drive mode (2) --3 acc lse (3) 3. this parameter depends on the crystal used in t he application. refer to application note an2867. lse accuracy - ? 500 - 500 ppm g m _crit_max maximum critical crystal g m low power mode (2) - - 0.56 a/v high drive mode (2) --1.5 t su(lse) (4) 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is based on characterization and not tested in production. it is measured for a standard crystal resonator and it can va ry significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - s dl 26&b28 7 26&b,1 i /6( & / 5 ) 670) n+ ] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq & /
electrical characteristics stm32f479xx 118/217 docid028010 rev 3 5.3.10 internal clock source characteristics the parameters given in table 39 and table 40 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 17 . high-speed internal (hsi) rc oscillator figure 33. acchsi vs. temperature 1. based on test during characterization. table 39. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hsi hsi user trimming step (2) 2. guaranteed by design ---1% hsi oscillator accuracy t a = ?40 to 105 c (3) 3. based on test during characterization. ? 8-4.5% t a = ?10 to 85 c (3) ? 4- 4 % t a = 25 c (4) 4. factory calibrated, parts not soldered. ? 1- 1 % t su(hsi) (2) hsi oscillator startup time - - 2.2 4 s i dd(hsi) (2) hsi oscillator power consumption - - 60 80 a 06y9 r? r re r? ? e re ?? ?? ?? ? ?? ,^/~9 d~ d]v d? d??]o
docid028010 rev 3 119/217 stm32f479xx electrical characteristics 190 low-speed internal (lsi) rc oscillator figure 34. acc lsi versus temperature 5.3.11 pll characteristics the parameters given in table 41 and table 42 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 17 . table 40. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on test during characterization. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design. startup time - 15 40 s i dd(lsi) (3) power consumption - 0.4 0.6 a -36 .ormalizeddeviati on 4emperat ure?# max avg min table 41. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) -0.95 (2) 12.10 mhz f pll_out pll multiplier output clock - 24 - 180 f pll48_out 48 mhz pll multiplier output clock - - 48 75 f vco_out pll vco output - 192 - 432
electrical characteristics stm32f479xx 120/217 docid028010 rev 3 t lock pll lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32- main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40- bit time can jitter cycle to cycle at 1 mhz on 1000 samples - 330 - i dd(pll) (4) pll power consumption on vdd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design. 3. the use of 2 plls in parallel can degrade the jitter up to +30%. 4. based on test during characterization. table 41. main pll characteristics (continued) symbol parameter conditions min typ max unit table 42. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) -0.95 (2) 12.10 mhz f plli2s_out plli2s multiplier output clock ---216 f vco_out plli2s vco output - 192 - 432 t lock plli2s lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - - peak to peak - 280 - ps average frequency of 12.288 mhz, n=432, r=5 on 1000 samples -90-ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples - 400 - ps
docid028010 rev 3 121/217 stm32f479xx electrical characteristics 190 i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division factor m to have the specified pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. based on test during characterization. table 42. plli2s (audio pll) characteristics (continued) symbol parameter conditions min typ max unit table 43. pllsai (audio and lcd-tft pll) characteristics symbol parameter conditions min typ max unit f pllsai_in pllsai input clock (1) -0.95 (2) 12.10 mhz f pllsai_out pllsai multiplier output clock - - - 216 f vco_out pllsai vco output - 192 - 432 t lock pllsai lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) main sai clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps fs clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(pllsai) (4) pllsai power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pllsai) (4) pllsai power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. based on test during characterization.
electrical characteristics stm32f479xx 122/217 docid028010 rev 3 5.3.12 pll spread spec trum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 54 ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation dep th (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generat ed because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: table 44. sscg parameters constraint symbol parameter min typ max (1) 1. guaranteed by design. unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - - 2 15 ? 1- modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 == incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2.002%(peak) ==
docid028010 rev 3 123/217 stm32f479xx electrical characteristics 190 figure 35 and figure 36 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 35. pll output clock waveforms in center spread mode figure 36. pll output clock waveforms in down spread mode 5.3.13 mipi d-phy characteristics the parameters given in table 45 and table 46 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 17 . 069 )uhtxhqf\ 3//b287 7lph ) w prgh pg [w prgh pg 069 )uhtxhqf\ 3//b287 7lph ) w prgh [pg [w prgh table 45. mipi d-phy characteristics (1) symbol parameter conditions min typ max unit hi-speed input/outp ut characteristics u inst ui instantaneous - 2 - 12.5 ns
electrical characteristics stm32f479xx 124/217 docid028010 rev 3 v cmtx hs transmit common mode voltage - 150 200 250 mv | ? v cmtx | v cmtx mismatch when output is differential-1 or differential-0 ---5 |v od | hs transmit differential voltage - 140 200 270 | ? v od | v od mismatch when output is differential-1 or differential-0 ---14 v ohhs hs output high voltage - - - 360 z os single ended output impedance -405062.5 ? ? z os single ended output impedance mismatch ---10% t hsr & t hsf 20%-80% rise and fall time - 100 - 0.35*ui ps lp receiver input characteristics v il logic 0 input voltage (not in ulp state) ---550 mv v il-ulps logic 0 input voltage in ulp state ---300 v ih input high level voltage - 880 - - v hys voltage hysteresis - 25 - - lp emitter output characteristics v il output low level voltage - 1.1 1.2 1.2 v v il-ulps output high level voltage - -50 - 50 mv v ih output impedance of lp transmitter -110-- ? v hys 15%-85% rise and fall time - - - 25 ns lp contention detector characteristics v ilcd logic 0 contention threshold - - - 200 mv v ihcd logic 0 contention threshold - 450 - - 1. guaranteed based on test during characterization. table 45. mipi d-phy characteristics (1) (continued) symbol parameter conditions min typ max unit
docid028010 rev 3 125/217 stm32f479xx electrical characteristics 190 table 46. mipi d-phy ac characteristics lp mode and hs/lp transitions (1) 1. guaranteed based on test during characterization. symbol parameter conditions min typ max unit t lpx transmitted length of any low- power state period -50-- ns t clk-prepare time that the transmitter drives the clock lane lp-00 line state immediately before the hs-0 line state starting the hs transmission. -38-95 t clk-prepare + t clk-zero time that the transmitter drives the hs-0 state prior to starting the clock. - 300 - - t clk-pre time that the hs clock shall be driven by the transmitter prior to any associated data lane beginning the transition from lp to hs mode. -8--ui t clk-post time that the transmitter continues to send hs clock after the last a ssociated data lane has transitioned to lp mode. -62+52*ui-- ns t clk-trail time that the transmitter drives the hs-0 state after the last payload clock bit of an hs transmission burst. -60-- t hs-prepare time that the transmitter drives the data lane lp-00 line state immediately before the hs-0 line state starting the hs transmission. - 40+4*ui - 85+6*ui t hs-prepare + t hs-zero t hs-prepare+ time that the transmitter drives the hs-0 state prior to transmitting the sync sequence. - 145+10*ui - - t hs-trail time that the transmitter drives the flipped differential state after last payload data bit of a hs transmission burst. - max (n*8*ui, 60+n*4*ui) -- t hs-exit time that the transmitter drives lp-11 following a hs burst. - 100 - - t reot 30%-85% rise time and fall time - - - 35 t eot transmitted time interval from the start of t hs-trail or t clk-trail , to the start of the lp-11 state following a hs burst. --- 105+ n*12ui
electrical characteristics stm32f479xx 126/217 docid028010 rev 3 figure 37. mipi d-phy hs/lp clock lane transition timing diagram figure 38. mipi d-phy hs/lp data lane transition timing diagram 5.3.14 mipi d-phy pll characteristics the parameters given in table 47 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 17 . 069 &orfn /dqh 'dwd /dqh 7 /3; 7 +635(3$5( 7 &/.35( 7 &/.=(52 7 &/.35(3$5( 7 /3; 7 +6(;,7 7 &/.75$,/ 7 &/.3267 9 ,/ 9 ,/ 7 (27 069 &orfn /dqh 7 +635(3$5( 7 /3; 7 +675$,/ 7 +6(;,7 /3 /3 /3 'dwd /dqh 9 ,/ 7 5(27 7 (27 7 +6=(52 table 47. dsi-pll characteristics (1) symbol parameter condi tions min typ max unit f pll_in pll input clock - 4 - 100 mhz f pll_infin pfd input clock - 4 - 25 f pll_out pll multiplier output clock - 31.25 - 500 f vco_out pll vco output - 500 - 1000 t lock pll lock time - - - 200 s
docid028010 rev 3 127/217 stm32f479xx electrical characteristics 190 5.3.15 mipi d-phy re gulator characteristics the parameters given in table 48 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 17 . i dd(pll) pll power consumption on v dd12 f vco_out = 500 mhz - 0.55 0.70 ma f vco_out = 600 mhz - 0.65 0.80 f vco_out = 1000 mhz - 0.95 1.20 1. based on test during characterization. table 47. dsi-pll characteristics (1) (continued) symbol parameter condi tions min typ max unit table 48. dsi regulator characteristics (1) symbol parameter conditions min typ max unit v dd12dsi 1.2 v internal voltage on v dd12dsi - 1.15 1.20 1.30 v c ext external capacitor on v capdsi - 1.1 2.2 3.3 f esr external serial resistor - 0 25 600 m ? i dddsireg regulator power consumption - 100 120 125 a i dddsi dsi system (regulator, pll and d-phy) current consumption on v dddsi ultra low power mode (reg. on + pll off) -290600 a stop state (reg. on + pll off) -290600 i dddsilp dsi system current consumption on v dddsi in lp mode communication (2) 10 mhz escape clock (reg. on + pll off) -4.35.0 ma 20 mhz escape clock (reg. on + pll off) -4.35.0 i dddsihs dsi system (regulator, pll and d-phy) current consumption on v dddsi in hs mode communication (3) 300 mbps - 1 data lane (reg. on + pll on) -8.08.8 ma 300 mbps - 2data lane (reg. on + pll on) - 11.4 12.5 500 mbps - 1 data lane (reg. on + pll on) -13.514.7 500 mbps - 2data lane (reg. on + pll on) -18.019.6 dsi system (regulator, pll and d-phy) current consumption on v dddsi in hs mode with clk like payload 500 mbps - 2data lane (reg. on + pll on) -21.423.3 t wakeup startup delay c ext = 2.2 f - 110 - s c ext = 3.3 f - - 160 i inrush inrush current on v dddsi external capacitor load at start - 60 200 ma 1. based on test during characterization. 2. values based on an average traffic in lp command mode. 3. values based on an average traffic (3/4 hs traffic & 1/4 lp) in video mode.
electrical characteristics stm32f479xx 128/217 docid028010 rev 3 5.3.16 memory characteristics flash memory the characteristics are given at ta = ?40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. table 49. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.7 v - 5 - ma write / erase 16-bit mode, v dd = 2.1 v - 8 - write / erase 32-bit mode, v dd = 3.3 v - 12 - table 50. flash memory programming symbol parameter conditions min (1) typ max (1) unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12
docid028010 rev 3 129/217 stm32f479xx electrical characteristics 190 t me mass erase time program/erase parallelism (psize) = x 8 -1632 s program/erase parallelism (psize) = x 16 -1122 program/erase parallelism (psize) = x 32 -816 t be bank erase time program/erase parallelism (psize) = x 8 -1632 program/erase parallelism (psize) = x 16 -1122 program/erase parallelism (psize) = x 32 -816 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 8-bit program operation 1.7 - 3.6 1. based on test during characterization. 2. the maximum programming time is m easured after 100k erase operations. table 51. flash memory programming with v pp symbol parameter conditions min (1) typ max (1) 1. guaranteed by design. unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v -16100 (2) 2. the maximum programming time is measured after 100k erase operations. s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 6.9 - s t be bank erase time - - 6.9 - s v prog programming voltage - 2.7 - 3.6 v v pp v pp voltage range - 7 - 9 i pp minimum current sunk on the v pp pin -10--ma t vpp (3) 3. v pp should only be connected during programming/erasing. cumulative time during which v pp is applied - - - 1 hour table 50. flash memory programming (continued) symbol parameter conditions min (1) typ max (1) unit
electrical characteristics stm32f479xx 130/217 docid028010 rev 3 table 52. flash memory endurance and data retention 5.3.17 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 53 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. symbol parameter conditions value unit min (1) 1. based on test during characterization. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 53. ems characteristics symbol parameter con ditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, tfbga216, t a = +25 c, f hclk = 168 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, tfbga216, t a = +25 c, f hclk = 168 mhz, conforming to iec 61000-4-2 4a
docid028010 rev 3 131/217 stm32f479xx electrical characteristics 190 software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc ? code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. 5.3.18 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/esd a/jedec js-001 and ansi /esd s5.3.1 standards. table 54. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 8/168 mhz 8/180 mhz s emi peak level v dd = 3.3 v, t a = 25 c, tfbga216 package, conforming to sae j1752/3 eembc, art on, all peripheral clocks enabled, clock dithering disabled. 0.1 to 30 mhz 2 2 dbv 30 to 130 mhz 4 1 130 mhz to 1ghz 10 10 sae emi level 3 3 - v dd = 3.3 v, t a = 25 c, tfbga216 package, conforming to sae j1752/3 eembc, art on, all peripheral clocks enabled, clock dithering enabled 0.1 to 30 mhz 5 -10 dbv 30 to 130 mhz 3 -15 130 mhz to 1ghz 8 0 sae emi level 2 2 -
electrical characteristics stm32f479xx 132/217 docid028010 rev 3 static latchup two complementary static te sts are required on six pa rts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. 5.3.19 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induc ed leakage current on adjacent pins (out of ? 5 a/+0 a range), or other f unctional failure (for exampl e reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 57 . table 55. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to ansi/esda/jedec js-001 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to ansi/esd s5.3.1, lqfp176, lqfp208, ufbga169, ufbga176, tfbga216 and wlcsp148 packages c3 250 1. guaranteed based on test during characterization. table 56. electri cal sensitivities (1) symbol parameter c onditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a 1. msv on pa4 and pa5 is 5 v, versus 5.4 v on all ios.
docid028010 rev 3 133/217 stm32f479xx electrical characteristics 190 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 5.3.20 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 58 are derived from tests performed under the conditions summarized in table 17 . all i/os are cmos and ttl compliant. table 57. i/o current injection susceptibility (1) 1. na = not applicable . symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 and nrst pins ? 0na ma injected current on dsihost_d0p, dsihost_d0n, dsihost_d1p, dsihost_d0n, dsihost_ckp, dsihost_ckn pins ? 00 injected current on pa0 and pc0 pins ? 0na injected current on any other ft pin ? 5na injected current on any other pin ? 5+ 5 table 58. i/o static characteristics symbol parameter conditions min typ max unit v il ft, tta and nrst i/o input low level voltage 1.7 v v dd 3.6 v - - 0.35v dd ? 0.04 (1) v 0.3v dd (2) boot0 i/o input low level voltage 1.75 v v dd 3.6 v, ?40 c t a 105 c -- 0.1v dd +0.1 (1) 1.7 v v dd 3.6 v, 0c t a 105 c -- v ih ft, tta and nrst i/o input high level voltage (5) 1.7 v v dd 3.6 v 0.45v dd +0.3 (1) -- 0.7v dd (2) boot0 i/o input high level voltage 1.75 v v dd 3.6 v, ?40 c t a 105 c 0.17v dd +0.7 (1) -- 1.7 v v dd 3.6 v, 0c t a 105 c
electrical characteristics stm32f479xx 134/217 docid028010 rev 3 v hys ft, tta and nrst i/o input hysteresis 1.7 v v dd 3.6 v 10%v dd (3) -- v boot0 i/o input hysteresis 1.75 v v dd 3.6 v, ? 40 c t a 105 c 0.1 - - 1.7 v v dd 3.6 v, 0c t a 105 c i lkg i/o input leakage current (4) v ss v in v dd -- 1 a i/o ft input leakage current (5) v in = 5v --3 r pu weak pull-up equivalent resistor (6) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v ss 30 40 50 k pa10/pb12 (otg_fs_id, otg_hs_id) 71014 r pd weak pull- down equivalent resistor (7) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v dd 30 40 50 pa10/pb12 (otg_fs_id, otg_hs_id) 71014 c io (8) i/o pin capacitance - - 5 - pf 1. guaranteed by design. 2. tested in production. 3. with a minimum of 200 mv. 4. leakage could be higher than the maximum value, if negat ive current is injected on adjacent pins, refer to table 57 5. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors mu st be disabled. leakage could be higher than the maximum value, if negative curr ent is injected on adjacent pins.refer to table 57 6. pull-up resistors are designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance is minimum (~10% order). 7. pull-down resistors are designed with a true resistance in se ries with a switchable nmos. th is nmos contribution to the series resistance is minimum (~10% order). 8. hysteresis voltage between schmitt trigger switchi ng levels. based on test during characterization. table 58. i/o static characteristics (continued) symbol parameter conditions min typ max unit
docid028010 rev 3 135/217 stm32f479xx electrical characteristics 190 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft i/os is shown in figure 39 . figure 39. ft i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14, pc15 and pi8 which can sink or source up to 3ma. when using the pc13 to pc15 and pi8 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 5.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 15 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 15 ). 069 9''9 9,/9,+9 7hvwhglqsurgxfwlrq&026uhtxluhphqw9,+plq 9'' 7hvwhglqsurgxfwlrq&026uhtxluhphqw9,/pd[ 9'' %dvhgrq'hvljqvlpxodwlrqv9,/pd[ 9'' 77/uhtxluhphqw 9,+plq 9 77/uhtxluhphqw9,/pd[ 9 $uhdqrw ghwhuplqhg %dvhgrq'hvljqvlpxodwlrqv9,+plq 9''
electrical characteristics stm32f479xx 136/217 docid028010 rev 3 output voltage levels unless otherwise specified, the parameters given in table 59 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . all i/os are cmos and ttl compliant. input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 40 and table 60 , respectively. unless otherwise specified, the parameters given in table 60 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 17 . table 59. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximum rating specified in table 15 . and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 15 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ? 0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+ 8ma 2.7 v v dd 3.6 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1) output low level voltage for an i/o pin i io = +20 ma 2.7 v v dd 3.6 v -1.3 (4) 4. based on characterization data. v oh (3) output high level voltage for an i/o pin v dd ? 1.3 (4) - v ol (1) output low level voltage for an i/o pin i io = +6 ma 1.8 v v dd 3.6 v -0.4 (4) v oh (3) output high level voltage for an i/o pin v dd ? 0.4 (4) - v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.7 v v dd 3.6v -0.4 (5) 5. guaranteed by design. v oh (3) output high level voltage for an i/o pin v dd ? 0.4 (5) -
docid028010 rev 3 137/217 stm32f479xx electrical characteristics 190 table 60. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 4 mhz c l = 50 pf, v dd 1.7 v - - 2 c l = 10 pf, v dd 2.7 v - - 8 c l = 10 pf, v dd 1.8 v - - 4 c l = 10 pf, v dd 1.7 v - - 3 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.7 v to 3.6 v --100ns 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 25 mhz c l = 50 pf, v dd 1.8 v - - 12.5 c l = 50 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 2.7 v - - 50 c l = 10 pf, v dd 1.8 v - - 20 c l = 10 pf, v dd 1.7 v - - 12.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd 2.7 v - - 10 ns c l = 10 pf, v dd 2.7 v - - 6 c l = 50 pf, v dd 1.7 v - - 20 c l = 10 pf, v dd 1.7 v - - 10 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd 2.7 v - - 50 (4) mhz c l = 10 pf, v dd 2.7 v - - 100 (4) c l = 40 pf, v dd 1.7 v - - 25 c l = 10 pf, v dd 1.8 v - - 50 c l = 10 pf, v dd 1.7 v - - 42.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd 2.7 v - - 6 ns c l = 10 pf, v dd 2.7 v - - 4 c l = 40 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 1.7 v - - 6
electrical characteristics stm32f479xx 138/217 docid028010 rev 3 figure 40. i/o ac charac teristics definition 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd 2.7 v - - 100 (4) mhz c l = 30 pf, v dd 1.8 v - - 50 c l = 30 pf, v dd 1.7 v - - 42.5 c l = 10 pf, v dd 2.7 v - - 180 (4) c l = 10 pf, v dd 1.8 v - - 100 c l = 10 pf, v dd 1.7 v - - 72.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd 2.7 v - - 4 ns c l = 30 pf, v dd 1.8 v - - 6 c l = 30 pf, v dd 1.7 v - - 7 c l = 10 pf, v dd 2.7 v - - 2.5 c l = 10 pf, v dd 1.8 v - - 3.5 c l = 10 pf, v dd 1.7 v - - 4 - textipw pulse width of external signals detected by the exti controller -10--ns 1. guaranteed by design. 2. the i/o speed is configured using the o speedry[1:0] bits. refer to the stm32f4x x reference manual fo r a description of the gpiox_speedr gpio port output speed register. 3. the maximum frequency is defined in figure 40 . 4. for maximum frequencies above 50 mhz and v dd > 2.4 v, the compensation cell should be used. table 60. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit dlg w u,2rxw 287387 (;7(51$/ 21&/ 0d[lpxpiuhtxhqf\lvdfklhyhgliw u w i ?7dqgliwkhgxw\f\fohlv zkhqordghge\& / vshflilhglqwkhwdeoh3 ,2$&fkdudfwhulvwlfv 7 w i,2rxw
docid028010 rev 3 139/217 stm32f479xx electrical characteristics 190 5.3.21 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 58 ). unless otherwise specified, the parameters given in table 61 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 17 . figure 41. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 61 . otherwise the reset is not taken into account by the device. table 61. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in = v ss 30 40 50 k v f(nrst) (2) nrst input filtered pulse - - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design. dlf 670) 5 38 1567 9 '' )lowhu ,qwhuqdo5hvhw ?) ([whuqdo uhvhwflufxlw
electrical characteristics stm32f479xx 140/217 docid028010 rev 3 5.3.22 tim time r characteristics the parameters given in table 62 are guaranteed by design. refer to section 5.3.20 for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). 5.3.23 communications interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s. the i 2 c timings requirements are guaranteed by de sign when the i2c peripheral is properly configured (refer to rm0386 reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. refer to section 5.3.20 for more details on the i 2 c i/o characteristics . all i 2 c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 62. timx characteristics (1)(2) 1. timx is used as a general term to refer to the tim1 to tim12 timers. 2. guaranteed by design. symbol parameter conditions (3) 3. the maximum timer frequency on apb1 or apb2 is up to 180 mhz, by setting the timpre bit in the rcc_dckcfgr register, if apbx prescaler is 1 or 2 or 4, then timxclk = hckl, otherwise timxclk = 4x pclkx. min max unit t res(tim) timer resolution time ahb/apbx prescaler=1 or 2 or 4, f timxclk = 180 mhz 1- t timxclk ahb/apbx prescaler>4, f timxclk = 90 mhz 1- t timxclk f ext timer external clock frequency on ch1 to ch4 f timxclk = 180 mhz 0 f timxclk /2 mhz res tim timer resolution - 16/32 bit t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk table 63. i2c analog filter characteristics (1) symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 150 (3) ns
docid028010 rev 3 141/217 stm32f479xx electrical characteristics 190 spi interface characteristics unless otherwise specified, the parameters given in table 64 for the spi interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 v dd refer to section 5.3.20 for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). 1. guaranteed based on test during characterization. 2. spikes with widths below t af(min) are filtered. 3. spikes with widths above t af(max) are not filtered table 64. spi dynamic characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode, 2.7 v v dd 3.6 v, spi1,4,5,6, --45 mhz master mode, 1.71 v v dd 3.6 v, spi1,4,5,6 - - 22.5 (2) master transmitter mode, 1.7 v v dd 3.6 v, spi1,4,5,6 --45 slave full duplex mode, 2.7 v v dd 3.6 v, spi1,4,5,6 - - 22.5 slave transmitter mode, 1.71 v v dd 3.6 v, spi1,4,5,6 --33 slave transmitter mode, 2.7 v v dd 3.6 v, spi1,4,5,6 --45 slave mode, 1.71 v v dd 3.6 v, spi2,3 - - 22.5 duty(sck) duty cycle of spi clock frequency slave mode 30 50 70 %
electrical characteristics stm32f479xx 142/217 docid028010 rev 3 t w(sckh) t w(sckl) sck high and low time master mode, spi presc = 2 t pclk ? 1.5 t pclk t pclk +1.5 ns t su(nss) nss setup time slave mode, spi presc = 2 4 t pclk -- t h(nss) nss hold time slave mode, spi presc = 2 2 t pclk t su(mi) data input setup time master mode 2 - - t su(si) slave mode 3 - - t h(mi) data input hold time master mode 4 - - t h(si) slave mode 2 - - t a(so ) data output access time slave mode, spi presc = 2 7 - 21 t dis(so) data output disable time slave mode 5 - 12 t v(so) data output valid time slave mode (after enable edge), 2.7v v dd 3.6v -1115 slave mode (after enable edge), 1.71 v v dd 3.6 v -1111.5 t h(so) data output hold time slave mode (after enable edge) 6 - - t v(mo) data output valid time master mode (after enable edge) - 4.5 5 t h(mo) data output hold time master mode (after enable edge) 2 - - 1. guaranteed based on test during characterization. 2. maximum frequency in slave transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value c an be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50% table 64. spi dynamic characteristics (1) (continued) symbol parameter conditions min typ max unit
docid028010 rev 3 143/217 stm32f479xx electrical characteristics 190 figure 42. spi timing diagram - slave mode and cpha = 0 figure 43. spi timing diagram - slave mode and cpha = 1 (1) ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
electrical characteristics stm32f479xx 144/217 docid028010 rev 3 figure 44. spi timing diagram - master mode (1) ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
docid028010 rev 3 145/217 stm32f479xx electrical characteristics 190 i 2 s interface characteristics unless otherwise specified, the parameters given in table 65 for the i 2 s interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 v dd refer to section 5.3.20 for more details on the input/output alternate function characteristics (ck, sd, ws). note: refer to the i2s section of rm0386 reference manual for more details on the sampling frequency (f s ). f mck , f ck , and d ck values reflect only the digital peripheral behavior, source clock precision might slightly change the values. the values of these parameters might be slightly impacted by the source clock precision. d ck depends mainly on the value of odd bit. the digital table 65. i 2 s dynamic characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256x8k 256xfs (2) mhz f ck i2s clock frequency master data - 64xfs slave data - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode 0 5 ns t h(ws) ws hold time master mode 0 - t su(ws) ws setup time slave mode 3.5 - slave mode pcm short pulse mode (3) 3.5 - t h(ws) ws hold time slave mode 0.5 - slave mode pcm short pulse mode (3) 1- t su(sd_mr) data input setup time master receiver 5 - t su(sd_sr) slave receiver 1.5 - t h(sd_mr) data input hold time master receiver 5 - t h(sd_sr) slave receiver 1.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 19 t v(sd_mt) master transmitter (after enable edge) - 2.50 t h(sd_st) data output hold time slave transmitter (after enable edge) 5 - t h(sd_mt) master transmitter (after enable edge) 0 - 1. guaranteed based on test during characterization. 2. 128xfs maximum is 24.756 mhz (apb1 maximum frequency). 3. measurement done with respect to i2s_ck rising edge.
electrical characteristics stm32f479xx 146/217 docid028010 rev 3 contribution leads to a minimum value of (i 2sdiv/(2*i2sdiv+odd) and a maximum value of (i2sdiv+odd)/(2* i2sdiv+odd). f s maximum value is supported for each mode/condition. figure 45. i 2 s slave timing diagram (philips protocol) (1) 1. .lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 46. i 2 s master timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14881b l s b receive (2) l s b tr a n s mit (2) ck output cpol = 0 cpol = 1 t c(ck) ws output sd receive sd transmit t w(ckh) t w(ckl) t su(sd_mr) t v(sd_mt) t h(sd_mt) t h(ws) t h(sd_mr) msb receive bitn receive lsb receive msb transmit bitn transmit lsb transmit ai14884b t f(ck) t r(ck) t v(ws) lsb receive (2) lsb transmit (2)
docid028010 rev 3 147/217 stm32f479xx electrical characteristics 190 sai characteristics unless otherwise specified, the parameters given in table 66 for sai are derived from tests performed under the ambient temperature, f pclkx frequency and vdd supply voltage conditions su mmarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c=30 pf ? measurement points are performed at cmos levels: 0.5 v dd refer to section 5.3.20 for more details on the input/output alternate function characteristics (sck,sd,ws). table 66. sai characteristics (1) symbol parameter conditions min max unit f mckl sai main clock output - 256 x 8k 256xfs mhz f ck sai clock frequency (2) master data: 32 bits - 128xfs (3) slave data: 32 bits - 128xfs t v(fs) fs valid time master mode, 2.7v v dd 3.6v -17 ns master mode, 1.71v v dd 3.6v -23 t su(fs) fs setup time slave mode 10 - t h(fs) fs hold time slave mode 0 - t su(sd_mr) data input setup time master receiver 1 - t su(sd_sr) slave receiver 2 - t h(sd_mr) data input hold time master receiver 6 - t h(sd_sr) slave receiver 1 - t h(sd_b_st) data output valid time slave transmitter (after enable edge), 2.7v v dd 3.6v -14 slave transmitter (after enable edge), 1.71v v dd 3.6v -23 t h(sd_b_st) data output hold time slave transmitter (after enable edge) 9 - t v(sd_a_mt) data output valid time master transmitter (after enable edge), 2.7v v dd 3.6v -20 master transmitter (after enable edge), 1.71v v dd 3.6v -26 t h(sd_a_mt) data output hold time master transmitter (after enable edge) 10 - 1. guaranteed based on test during characterization. 2. apb clock frequency must be at least twice sai clock frequency. 3. with fs = 192 khz.
electrical characteristics stm32f479xx 148/217 docid028010 rev 3 figure 47. sai master timing waveforms figure 48. sai slave timing waveforms -36 3!)?3#+?8 3!)?&3?8 output f 3#+ 3!)?3$?8 transmit t v&3 3lotn 3!)?3$?8 receive t h&3 3lotn t v3$?-4 t h3$?-4 3lotn t su3$?-2 t h3$?-2 -36 3!)?3#+?8 3!)?&3?8 input 3!)?3$?8 transmit t su&3 3lotn 3!)?3$?8 receive t w#+(?8 t h&3 3lotn t v3$?34 t h3$?34 3lotn t su3$?32 t w#+,?8 t h3$?32 f 3#+
docid028010 rev 3 149/217 stm32f479xx electrical characteristics 190 usb otg full speed (fs) characteristics this interface is present in both the usb otg hs and usb otg fs controllers. note: when vbus sensing feature is enabled, pa9 and pb13 should be left at their default state (floating input), not as alternate function. a typical 200 a current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on pa9 and pb13 when the feature is enabled. table 67. usb otg full speed startup time symbol parameter max unit t startup (1) 1. guaranteed by design. usb otg full speed transceiver startup time 1 s table 68. usb otg full speed dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg full speed transceiver operating voltage -3.0 (2) 2. the usb otg full speed transceiver functionality is ensured down to 2.7 v but not the full usb full speed electrical charac teristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6 v v di (3) 3. guaranteed by design. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold - 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg full speed drivers. --0.3 v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55
electrical characteristics stm32f479xx 150/217 docid028010 rev 3 figure 49. usb otg full speed timings: definition of data signal rise and fall time usb high speed (hs) characteristics unless otherwise specified, the parameters given in table 72 for ulpi are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 71 and v dd supply voltage cond itions summarized in table 70 , with the following configuration: ? output speed is set to ospeedry[1:0 ] = 11, unless otherwise specified ? capacitive load c = 20 pf / 15 pf, unless otherwise specified ? measurement points are done at cmos levels: 0.5 v dd . refer to section 5.3.20 for more details on the i nput/output characteristics. table 69. usb otg full speed electrical characteristics (1) 1. guaranteed by design. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420 ns t f fall time (2) c l = 50 pf 4 20 t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crosso ver voltage - 1.3 2.0 v z drv output driver impedance (3) 3. no external termination series resistors are requ ired on dp (d+) and dm (d-) pins since the matching impedance is included in the embedded driver. driving high or low 28 44 table 70. usb hs dc elect rical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd usb otg hs operating voltage 1.7 3.6 v ai14137 t f differen tial data l ines v ss v cr s t r crossover points
docid028010 rev 3 151/217 stm32f479xx electrical characteristics 190 figure 50. ulpi timing diagram table 71. usb hs cloc k timing parameters (1) 1. guaranteed by design. symbol parameter min typ max unit - f hclk value to guarantee proper operation of usb hs interface 30 - - mhz f start_8bit frequency (first transition) 8-bit 10% 54 60 66 f steady frequency (steady state) 500 ppm 59.97 60 60.03 d start_8bit duty cycle (first transition) 8-bit 10% 40 50 60 % d steady duty cycle (steady state) 500 ppm 49.975 50 50.025 t steady time to reach the steady state frequency and duty cycle after the first transition --1.4ms t start_dev clock startup time after the de-assertion of suspendm peripheral - - 5.6 ms t start_host host - - - t prep phy preparation time after the first transition of the input clock ---s #lock #ontrol)n 5,0)?$)2 5,0)?.84 data)n bit #ontrolout 5,0)?340 dataout bit t $$ t $# t ($ t 3$ t (# t 3# aic t $#
electrical characteristics stm32f479xx 152/217 docid028010 rev 3 ethernet characteristics unless otherwise specified, the parameters given in table 73 , table 74 and table 75 for smi, rmii and mii are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 v dd . refer to section 5.3.20 for more details on the i nput/output characteristics. table 73 gives the list of ethernet mac signals for the smi (station management interface) and figure 51 shows the corresponding timing diagram. figure 51. ethernet smi timing diagram table 72. dynamic characteristics: usb ulpi (1) 1. guaranteed based on test during characterization. symbol parameter conditions min. typ. max. unit t sc control in (ulpi_dir, ulpi_nxt) setup time -2.0-- ns t hc control in (ulpi_dir, ulpi_nxt) hold time -1.5-- t sd data in setup time - 1.0 - - t hd data in hold time - 1.0 - - t dc /t dd data/control output delay 2.7 v < v dd < 3.6 v, c l = 20 pf -7.59.0 2.7 v < v dd < 3.6 v, c l = 15 pf and -40 < t < 125c - 7.5 12.0 1.7 v < v dd < 3.6 v, c l = 15 pf and -40 < t < 90c -7.511.5 069 (7+b0'& (7+b0',22 (7+b0',2, w0'& wg0',2 wvx0',2 wk0',2
docid028010 rev 3 153/217 stm32f479xx electrical characteristics 190 table 74 gives the list of ethernet mac signals for the rmii and figure 52 shows the corresponding timing diagram. figure 52. ethernet rmii timing diagram table 73. dynamics characteristics: ethernet mac signals for smi (1) 1. guaranteed based on test during characterization. symbol parameter min typ max unit t mdc mdc cycle time(2.38 mhz) 400 400 403 ns t d(mdio) write data valid time t hclk - 1 t hclk t hclk + 1.5 t su(mdio) read data setup time 12.5 - - t h(mdio) read data hold time 0 - - rmii_ref_clk rmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667
electrical characteristics stm32f479xx 154/217 docid028010 rev 3 table 75 gives the list of ethernet mac signals for mii and figure 52 shows the corresponding timing diagram. figure 53. ethernet mii timing diagram table 74. dynamics characteristi cs: ethernet mac signals for rmii (1) 1. guaranteed based on test during characterization. symbol parameter min typ max unit t su(rxd) receive data setup time 2.5 - - ns t ih(rxd) receive data hold time 2.0 - - t su(crs) carrier sense setup time 0.5 - - t ih(crs) carrier sense hold time 1.5 - - t d(txen) transmit enable valid delay time 5.5 6.5 11 t d(txd) transmit data valid delay time 6.0 6.5 11 table 75. dynamics characteristics: ethernet mac signals for mii (1) 1. guaranteed based on test during characterization. symbol parameter min typ max unit t su(rxd) receive data setup time 1 - - ns t ih(rxd) receive data hold time 3 - - t su(dv) data valid setup time 0 - - t ih(dv) data valid hold time 2.5 - - t su(er) error setup time 0 - - t ih(er) error hold time 2 - - t d(txen) transmit enable valid delay time 0 7 13 t d(txd) transmit data valid delay time 0 7 13 mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(dv) t ih(rxd) t ih(er) t ih(dv) ai1566 8 mii_tx_clk mii_tx_en mii_txd[3:0]
docid028010 rev 3 155/217 stm32f479xx electrical characteristics 190 can (controller area network) interface refer to section 5.3.20 for more details on the input/output alternate function characteristics (canx_tx and canx_rx). 5.3.24 12-bit adc characteristics unless otherwise specified, the parameters given in table 76 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 17 . table 76. adc characteristics symbol parameter conditions min typ max unit v dda power supply v dda ? v ref+ < 1.2 v 1.7 (1) -3.6 v v ref+ positive reference voltage 1.7 (1) -v dda v ref- negative reference voltage - 0 - f adc adc clock frequency v dda = 1.7 (1) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v 0.6 30 36 f trig (2) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz ---171/f adc v ain conversion voltage range (3) - 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance details in equation 1 --50k r adc (2)(4) sampling switch resistance - - - 6 k c adc (2) internal sample and hold capacitor --47pf t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s ---3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s - 3 - 480 1/f adc t stab (2) power-up time - - 2 3 s
electrical characteristics stm32f479xx 156/217 docid028010 rev 3 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 f adc = 30 mhz 8-bit resolution 0.37 - 16.27 f adc = 30 mhz 6-bit resolution 0.30 - 16.20 9 to 492 (t s for sampling +n-bit resolution for successive approximation) 1/f adc f s (2) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc --2 msps 12-bit resolution interleave dual adc mode --3.75 12-bit resolution interleave triple adc mode --6 i vref+ (2) adc v ref dc current consumption in conversion mode - - 300 500 a i vdda (2) adc v dda dc current consumption in conversion mode --1.61.8ma 1. v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 2.19.2 ). 2. based on test during characterization. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.7 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 76 . table 76. adc characteristics (continued) symbol parameter conditions min typ max unit r ain k0.5 ? () f adc c adc 2 n 2 + () ln ---------------------------------------------------------------- r adc ? =
docid028010 rev 3 157/217 stm32f479xx electrical characteristics 190 a table 77. adc static accuracy at f adc = 18 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. based on test during characterization. unit et total unadjusted error f adc =18 mhz v dda = 1.7 to 3.6 v v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 3 4 lsb eo offset error 2 3 eg gain error 1 3 ed differential linearity error 1 2 el integral linearity error 2 3 table 78. adc static accuracy at f adc = 30 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. based on test during characterization. unit et total unadjusted error f adc = 30 mhz, r ain < 10 k , v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v, v dda ? v ref < 1.2 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 table 79. adc static accuracy at f adc = 36 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. based on test during characterization. unit et total unadjusted error f adc =36 mhz, v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 4 7 lsb eo offset error 2 3 eg gain error 3 6 ed differential linearity error 2 3 el integral linearity error 3 6
electrical characteristics stm32f479xx 158/217 docid028010 rev 3 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.20 does not affect the adc accuracy. table 80. adc dynamic accuracy at f adc = 18 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =18 mhz v dda = v ref+ = 1.7 v input frequency = 20 khz temperature = 25 c 10.3 10.4 - bits sinad signal-to-noise and distortion ratio 64 64.2 - db snr signal-to-noise ratio 64 65 - thd total harmonic distortion ? 67 ? 72 - 1. guaranteed based on test during characterization. table 81. adc dynamic accuracy at f adc = 36 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =36 mhz v dda = v ref+ = 3.3 v input frequency = 20 khz temperature = 25 c 10.6 10.8 - bits sinad signal-to noise and distortion ratio 66 67 - db snr signal-to noise ratio 64 68 - thd total harmonic distortion ? 70 ? 72 - 1. guaranteed based on test during characterization.
docid028010 rev 3 159/217 stm32f479xx electrical characteristics 190 figure 54. adc accuracy characteristics 1. see also table 78 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. figure 55. typical connecti on diagram using the adc 1. refer to table 76 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. aic % / % ' , 3" )$%!, % 4 % $ % , 6 $$! 6 33! 6 2%& ordependingonpackage = 6 $$! ;,3" )$%!, dl 670) 9 '' $,1[ , / ??$ 9 9 7 5 $,1 & sdudvlwlf 9 $,1 9 9 7 5 $'& & $'& elw frqyhuwhu 6dpsohdqgkrog$'& frqyhuwhu
electrical characteristics stm32f479xx 160/217 docid028010 rev 3 general pcb design guidelines power supply decoupling should be performed as shown in figure 56 or figure 57 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 56. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176 and tfbga216. v ref+ is also available on lqfp176 and lqfp208. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . figure 57. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176 and tfbga216. v ref+ is also available on lqfp176 and lqfp208. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . 069 670) ?)q) ?)q) 95() 966$95() 9''$ 069 670) ?)q) 95()9''$ 95()9''$
docid028010 rev 3 161/217 stm32f479xx electrical characteristics 190 5.3.25 temperature sensor characteristics 5.3.26 v bat monitoring characteristics 5.3.27 reference voltage the parameters given in table 85 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . table 82. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 - mv/c v 25 (1) voltage at 25 c - 0.76 - v t start (2) startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature (1 c accuracy) 10 - - 1. based on test during characterization. 2. guaranteed by design. table 83. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff 7a2c - 0x1fff 7a2d ts_cal2 ts adc raw data acquired at temperature of 110 c, v dda = 3.3 v 0x1fff 7a2e - 0x1fff 7a2f table 84. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 4 - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design. 2. shortest sampling time can be determined in the application by multiple iterations. table 85. internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage 10 - - s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3v 10mv - 3 5 mv
electrical characteristics stm32f479xx 162/217 docid028010 rev 3 5.3.28 dac electri cal characteristics t coeff (2) temperature coefficient - 30 50 ppm/c t start (2) startup time - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design table 85. internal reference voltage (continued) symbol parameter conditions min typ max unit table 86. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c vdda = 3.3 v 0x1fff 7a2a - 0x1fff 7a2b table 87. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 1.7 (1) -3.6 v - v ref+ reference supply voltage 1.7 (1) -3.6vv ref+ v dda v ssa ground 0- 0v - r load (2) resistive load with buffer on 5 - - k - r o (2) impedance output with buffer off --15k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.7 v dac_out max (2) higher dac_out voltage with buffer on -- v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off -- v ref+ ? 1lsb v i vref+ (4) dac dc v ref current consumption in quiescent mode (standby mode) -170240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs -5075 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs
docid028010 rev 3 163/217 stm32f479xx electrical characteristics 190 i dda (4) dac dc vdda current consumption in quiescent mode (3) -280380a with no load, middle code (0x800) on the inputs -475625a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (4) differential non linearity difference between two consecutive code-1lsb) - - 0.5 lsb given for the dac in 10-bit configuration. - - 2 lsb given for the dac in 12-bit configuration. inl (4) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) - - 1 lsb given for the dac in 10-bit configuration. - - 4 lsb given for the dac in 12-bit configuration. offset (4) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) - - 10 mv given for the dac in 12-bit configuration --3lsb given for the dac in 10-bit at v ref+ = 3.6 v --12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (4) gain error - - 0.5 % given for the dac in 12-bit configuration t settling (4) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb -3 6s c load 50 pf, r load 5 k thd (4) total harmonic distortion buffer on -- -db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1ms/s c load 50 pf, r load 5 k t wakeup (4) wakeup time from off state (setting the enx bit in the dac control register) -6.510s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - ?67 ?40 db no r load , c load = 50 pf 1. v dda minimum value of 1.7 v is obtained with the use of an external power suppl y supervisor (refer to section 2.19.2 ). 2. guaranteed by design. 3. the quiescent mode corresponds to a state where the dac maintains a stable output level to ensure that no dynamic consumption occurs. 4. guaranteed based on test during characterization. table 87. dac characteristics (continued) symbol parameter min typ max unit comments
electrical characteristics stm32f479xx 164/217 docid028010 rev 3 figure 58. 12-bit buffered/non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 5.3.29 fmc characteristics unless otherwise specified, th e parameters given in tables 88 through 101 for the fmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? measurement points are done at cmos levels: 0.5 v dd refer to section 5.3.20 for more details on the input/output characteristics. asynchronous waveforms and timings figures 59 through 62 represent asynchronous waveforms, and tables 88 through 95 provide the corresponding timings. the result s shown in these tables are obtained with the following fmc configuration: ? addresssetuptime = 0x1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 (except for asynchronous nwait mode , datasetuptime = 0x5) ? busturnaroundduration = 0x0 ? capacitive load c l = 30 pf 5 / & / %xiihuhg1rqexiihuhg'$& '$&b287[ %xiihu elw gljlwdowr dqdorj frqyhuwhu dl9
docid028010 rev 3 165/217 stm32f479xx electrical characteristics 190 figure 59. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. $ata &-#?.% &-#?.",;= &-#?$;= t v",?.% t h$ata?.% &-#?./% !ddress &-#?!;= t v!?.% &-#?.7% t su$ata?.% t w.% -36 w./% t t v./%?.% t h.%?./% t h$ata?./% t h!?./% t h",?./% t su$ata?./% &-#?.!$6 t v.!$6?.% t w.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
electrical characteristics stm32f479xx 166/217 docid028010 rev 3 table 88. asynchronous non-multiplexed sram/psram/nor - read timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 2t hclk ? 0.5 2 t hclk +0.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 0 1 t w(noe) fmc_noe low time 2t hclk 2t hclk + 0.5 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 2 t h(a_noe) address hold time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t h(bl_noe) fmc_bl hold time after fmc_noe high 0 - t su(data_ne) data to fmc_nex high setup time t hclk + 2.5 - t su(data_noe) data to fmc_noex high setup time t hclk +2 - t h(data_noe) data hold time after fmc_noe high 0 - t h(data_ne) data hold time after fmc_nex high 0 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 t w(nadv) fmc_nadv low time - t hclk +1 table 89. asynchronous non-multipl exed sram/psram/nor read - nwait timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 7t hclk +0.5 7t hclk +1 ns t w(noe) fmc_nwe low time 5t hclk ? 1.5 5t hclk +2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 -
docid028010 rev 3 167/217 stm32f479xx electrical characteristics 190 figure 60. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. table 90. asynchronous non-multiplexed sram/psram/nor write timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk 3t hclk +1 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk ? 0.5 t hclk + 0.5 t w(nwe) fmc_nwe low time t hclk t hclk + 0.5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk +1.5 - t v(a_ne) fmc_nex low to fmc_a valid - 0 t h(a_nwe) address hold time after fmc_nwe high t hclk +0.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 1.5 t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk +0.5 - t v(data_ne) data to fmc_nex low to data valid - t hclk + 2 t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0.5 t w(nadv) fmc_nadv low time - t hclk + 0.5 .", $ata &-#?.%x &-#?.",;= &-#?$;= t v",?.% t h$ata?.7% &-#?./% !ddress &-#?!;= t v!?.% t w.7% &-#?.7% t v.7%?.% t h.%?.7% th!?.7% t h",?.7% t v$ata?.% t w.% -36 &-#?.!$6 t v.!$6?.% t w.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
electrical characteristics stm32f479xx 168/217 docid028010 rev 3 figure 61. asynchronous multiplexed psram/nor read waveforms table 91. asynchronous non-multiplexed sram/psram/nor write - nwait timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk +1 8t hclk +2 ns t w(nwe) fmc_nwe low time 6t hclk ? 16t hclk +2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 - .", $ata &-#? .",;= &-#? !$;= t v",?.% t h$ata?.% !ddress &-#? !;= t v!?.% &-#?.7% t v!?.% -36 !ddress &-#?.!$6 t v.!$6?.% t w.!$6 t su$ata?.% t h!$?.!$6 &-#? .% &-#?./% t w.% t w./% t v./%?.% t h.%?./% t h!?./% t h",?./% t su$ata?./% t h$ata?./% &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
docid028010 rev 3 169/217 stm32f479xx electrical characteristics 190 table 92. asynchronous multiplexed psram/nor read timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk ? 13t hclk +0.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 2t hclk ? 0.5 2t hclk t tw(noe) fmc_noe low time t hclk ? 1t hclk +1 t h(ne_noe) fmc_noe high to fmc_ne high hold time 1 - t v(a_ne) fmc_nex low to fmc_a valid - 2 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 2 t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk +0.5 t h(ad_nadv) fmc_ad(address) valid hold time after fmc_nadv high) 0 - t h(a_noe) address hold time after fmc_noe high t hclk ? 0.5 - t h(bl_noe) fmc_bl time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t su(data_ne) data to fmc_nex high setup time t hclk +1.5 - t su(data_noe) data to fmc_noe high setup time t hclk +1 - t h(data_ne) data hold time after fmc_nex high 0 - t h(data_noe) data hold time after fmc_noe high 0 - table 93. asynchronous multiplexed psram/nor read-nwait timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk +0.5 8t hclk +2 ns t w(noe) fmc_nwe low time 5t hclk ? 15t hclk +1.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 -
electrical characteristics stm32f479xx 170/217 docid028010 rev 3 figure 62. asynchronous multip lexed psram/nor write waveforms table 94. asynchronous multiplexed psram/nor write timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 4t hclk 4t hclk +0.5 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk ? 1t hclk +0.5 t w(nwe) fmc_nwe low time 2t hclk 2t hclk +0.5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk - t v(a_ne) fmc_nex low to fmc_a valid - 0 t v(nadv_ne) fmc_nex low to fmc_nadv low 0.5 1 t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk + 0.5 t h(ad_nadv) fmc_ad (address) valid hold time after fmc_nadv high t hclk ? 2- t h(a_nwe) address hold time after fmc_nwe high t hclk - t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk ? 2- t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t v(data_nadv) fmc_nadv high to data valid - t hclk +1.5 t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - .", $ata &-#? .%x &-#? .",;= &-#? !$;= t v",?.% t h$ata?.7% &-#?./% !ddress &-#? !;= t v!?.% t w.7% &-#?.7% t v.7%?.% t h.%?.7% t h!?.7% t h",?.7% t v!?.% t w.% -36 !ddress &-#?.!$6 t v.!$6?.% t w.!$6 t v$ata?.!$6 t h!$?.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
docid028010 rev 3 171/217 stm32f479xx electrical characteristics 190 synchronous waveforms and timings figures 63 through 66 represent synchronous waveforms and table 96 through table 99 provide the corresponding timings. the result s shown in these tables are obtained with the following fmc configuration: ? burstaccessmode = fmc_ burstaccessmode_enable; ? memorytype = fmc_memorytype_cram; ? writeburst = fmc_writeburst_enable; ? clkdivision = 1; ? datalatency = 1 for nor flash; datalatency = 0 for psram ? c l = 30 pf on data and address lines. c l = 10 pf on fmc_clk unless otherwise specified. in all timing tables, the t hclk is the hclk clock period: ? for 2.7 v v dd 3.6 v, maximum fmc_clk = 90 mhz at c l = 30 pf (on fmc_clk). ? for 1.71 v v dd <1.9 v, maximum fmc_clk = 60 mhz at c l = 10 pf (on fmc_clk). table 95. asynchronous multiplexed psram/nor write-nwait timings (1) 1. based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 9t hclk 9t hclk +0.5 ns t w(nwe) fmc_nwe low time 7t hclk 7t hclk +2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk ?1 -
electrical characteristics stm32f479xx 172/217 docid028010 rev 3 figure 63. synchronous multiplexed nor/psram read timings &-#?#,+ &-#?.%x &-#?.!$6 &-#?!;= &-#?./% &-#?!$;= !$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, td#,+( .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( td#,+( !)6 t d#,+, ./%, td#,+( ./%( t d#,+, !$6 t d#,+, !$)6 t su!$6 #,+( t h#,+( !$6 t su!$6 #,+( t h#,+( !$6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 -36
docid028010 rev 3 173/217 stm32f479xx electrical characteristics 190 table 96. synchronous multiple xed nor/psram read timings (1) 1. based on test during characterization. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 0 t d(clkh_nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-noel) fmc_clk low to fmc_noe low - t hclk +0.5 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk ? 0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 0.5 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t su(adv-clkh) fmc_a/d[15:0] valid data before fmc_clk high 5 - t h(clkh-adv) fmc_a/d[15:0] valid data after fmc_clk high 0 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 4 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 -
electrical characteristics stm32f479xx 174/217 docid028010 rev 3 figure 64. synchronous multiplexed psram write timings &-#?#,+ &-#?.%x &-#?.!$6 &-#?!;= &-#?.7% &-#?!$;= !$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+( .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+( !)6 t d#,+( .7%( t d#,+, .7%, t d#,+( .",( t d#,+, !$6 t d#,+, !$)6 t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 -36 t d#,+, $ata &-#?.",
docid028010 rev 3 175/217 stm32f479xx electrical characteristics 190 table 97. synchronous multiplexed psram write timings (1) 1. based on test during characterization. symbol parameter min max unit t w(clk) fmc_clk period, v dd range= 2.7 to 3.6 v 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0?2) - 1.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 0 t (clkh-nweh) fmc_clk high to fmc_nwe high t hclk ? 0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 3 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t d(clkl-data) fmc_a/d[15:0] valid data after fmc_clk low - 3 t d(clkl-nbll) fmc_clk low to fmc_nbl low 0 - t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk ? 0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 4 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 -
electrical characteristics stm32f479xx 176/217 docid028010 rev 3 figure 65. synchronous non-multiplexed nor/psram read timings table 98. synchronous non-multiplexed nor/psram read timings (1) 1. based on test during characterization. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 1 - ns t (clkl-nexl) fmc_clk low to fmc_nex low (x=0?2) - 0.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk ? 0.5 - t d(clkl-noel) fmc_clk low to fmc_noe low - t hclk +2 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk ? 0.5 - t su(dv-clkh) fmc_d[15:0] valid data before fmc_clk high 5 - t h(clkh-dv) fmc_d[15:0] valid data after fmc_clk high 0 - t (nwait-clkh) fmc_nwait valid before fmc_clk high 4 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 - &-#?#,+ &-#?.%x &-#?!;= &-#?./% &-#?$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency t d#,+, .%x, t d#,+( .%x( t d#,+, !6 t d#,+( !)6 t d#,+, ./%, t d#,+( ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 -36 &-#?.!$6 t d#,+, .!$6, t d#,+, .!$6(
docid028010 rev 3 177/217 stm32f479xx electrical characteristics 190 figure 66. synchronous non-multi plexed psram write timings table 99. synchronous non-multiplexed psram write timings (1) 1. based on test during characterization. symbol parameter min max unit t (clk) fmc_clk period 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0?2) - 0.5 t (clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 0 t d(clkh-nweh) fmc_clk high to fmc_nwe high t hclk ? 0.5 - t d(clkl-data) fmc_d[15:0] valid data after fmc_clk low - 2.5 t d(clkl-nbll) fmc_clk low to fmc_nbl low 0 - t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk ? 0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 4 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 - -36 &-#?#,+ &-#?.%x &-#?!;= &-#?.7% &-#?$;= $ $ &-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency t d#,+, .%x, t d#,+( .%x( t d#,+, !6 t d#,+( !)6 t d#,+( .7%( t d#,+, .7%, t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 &-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( t d#,+, $ata &-#?.", t d#,+( .",(
electrical characteristics stm32f479xx 178/217 docid028010 rev 3 nand controller waveforms and timings figures 67 through 70 represent synchronous waveforms, and table 100 and table 101 provide the corresponding timings. the results shown in this table are obtained with the following fmc configuration: ? com.fmc_setuptime = 0x01; ? com.fmc_waitsetuptime = 0x03; ? com.fmc_holdsetuptime = 0x02; ? com.fmc_hizsetuptime = 0x01; ? att.fmc_setuptime = 0x01; ? att.fmc_waitsetuptime = 0x03; ? att.fmc_holdsetuptime = 0x02; ? att.fmc_hizsetuptime = 0x01; ? bank = fmc_bank_nand; ? memorydatawidth = fmc_memorydatawidth_16b; ? ecc = fmc_ecc_enable; ? eccpagesize = fmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0; ? capacitive load c l = 30 pf. in all timing tables, the t hclk is the hclk clock period. figure 67. nand controller waveforms for read access &-#?.7% &-#?./%.2% &-#?$;= t su$ ./% t h./% $ -36 !,%&-#?! #,%&-#?! &-#?.#%x t d!,% ./% th./% !,%
docid028010 rev 3 179/217 stm32f479xx electrical characteristics 190 figure 68. nand controller waveforms for write access figure 69. nand controller waveforms for common memory read access -36 t h.7% $ t v.7% $ &-#?.7% &-#?./%.2% &-#?$;= !,%&-#?! #,%&-#?! &-#?.#%x t d!,% .7% t h.7% !,% -36 &-#?.7% &-#?./% &-#?$;= t w./% t su$ ./% t h./% $ !,%&-#?! #,%&-#?! &-#?.#%x t d!,% ./% t h./% !,%
electrical characteristics stm32f479xx 180/217 docid028010 rev 3 figure 70. nand controller wavefo rms for common memory write access sdram waveforms and timings ? c l = 30 pf on data and address lines. ? c l = 10 pf on fmc_sdclk unless otherwise specified. table 100. switching characteristics for nand flash read cycles symbol parameter min max unit t w(n0e) fmc_noe low width 4t hclk ? 0.5 4t hclk +0.5 ns t su(d-noe) fmc_d[15-0] valid data before fmc_noe high 9 - t h(noe-d) fmc_d[15-0] valid data after fmc_noe high 0 - t d(ale-noe) fmc_ale valid before fmc_noe low - 3t hclk ? 0.5 t h(noe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 2- table 101. switching characteristics for nand flash write cycles symbol parameter min max unit t w(nwe) fmc_nwe low width 4t hclk 4t hclk +1 ns t v(nwe-d) fmc_nwe low to fmc_d[15-0] valid 0 - t h(nwe-d) fmc_nwe high to fmc_d[15-0] invalid 3t hclk ? 1- t d(d-nwe) fmc_d[15-0] valid before fmc_nwe high 5t hclk ? 3- t d(ale-nwe) fmc_ale valid before fmc_nwe low - 3t hclk ? 0.5 t h(nwe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 1- -36 t w.7% t h.7% $ t v.7% $ &-#?.7% &-#?. /% &-#?$;= t d$ .7% !,%&-#?! #,%&-#?! &-#?.#%x t d!,% ./% t h./% !,%
docid028010 rev 3 181/217 stm32f479xx electrical characteristics 190 in all timing tables, the t hclk is the hclk clock period. ? for 2.7 v v dd 3.6 v, maximum fmc_sdclk = 90 mhz, at c l = 30 pf (on fmc_sdclk). ? for 1.71 v v dd <1.9 v, maximum fmc_sdclk = 75 mhz when cas latency = 3 and 60 mhz for cas latency 1 or 2. c l = 10 pf (on fmc_sdclk). figure 71. sdram read access waveforms (cl = 1) table 102. sdram read timings (1) 1. guaranteed based on test during characterization. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t su(sdclkh _data) data input setup time 2 - t h(sdclkh_data) data input hold time 0 - t d(sdclkl_add) address valid time - 1.5 t d(sdclkl- sdne) chip select valid time - 0.5 t h(sdclkl_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 0.5 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t h(sdclkl_sdncas) sdncas hold time 0 - -36 2own #ol &-#?3$#,+ &-#?! >@ &-#?3$.2!3 &-#?3$.#!3 &-#?3$.7% &-#?$;= &-#?3$.%;= td3$#,+,?!dd2 td3$#,+,?!dd# th3$#,+,?!dd2 th3$#,+,?!dd# td3$#,+,?3.$% tsu3$#,+(?$ata th3$#,+(?$ata #ol #oli #oln $ata $atai $atan $ata th3$#,+,?3.$% td3$#,+,?.2!3 td3$#,+,?.#!3 th3$#,+,?.#!3 th3$#,+,?.2!3
electrical characteristics stm32f479xx 182/217 docid028010 rev 3 figure 72. sdram write access waveforms table 103. lpsdr sdram read timings (1) 1. guaranteed based on test during characterization. symbol paramete r min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t su(sdclkh_data) data input setup time 2.5 - t h(sdclkh_data) data input hold time 0 - t d(sdclkl_add) address valid time - 1 t d(sdclkl_sdne) chip select valid time - 1 t h(sdclkl_sdne) chip select hold time 1 - t d(sdclkl_sdnras sdnras valid time - 1 t h(sdclkl_sdnras) sdnras hold time 1 - t d(sdclkl_sdncas) sdncas valid time - 1 t h(sdclkl_sdncas) sdncas hold time 1 - -36 2own #ol &-#?3$#,+ &-#?! >@ &-#?3$.2!3 &-#?3$.#!3 &-#?3$.7% &-#?$;= &-#?3$.%;= td3$#,+,?!dd2 td3$#,+,?!dd# th3$#,+,?!dd2 th3$#,+,?!dd# td3$#,+,?3.$% td3$#,+,?$ata th3$#,+,?$ata #ol #oli #oln $ata $atai $atan $ata th3$#,+,?3.$% td3$#,+,?.2!3 td3$#,+,?.#!3 th3$#,+,?.#!3 th3$#,+,?.2!3 td3$#,+,?.7% th3$#,+,?.7% &-#?.",;= td3$#,+,?.",
docid028010 rev 3 183/217 stm32f479xx electrical characteristics 190 table 104. sdram write timings (1) 1. guaranteed based on test during characterization. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t d(sdclkl _data ) data output valid time - 2.5 t h(sdclkl _data) data output hold time 3.5 - t d(sdclkl_add) address valid time - 1.5 t d(sdclkl_sdnwe) sdnwe valid time - 1 t h(sdclkl_sdnwe) sdnwe hold time 0 - t d(sdclkl_ sdne) chip select valid time - 0.5 t h(sdclkl-_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 2 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t d(sdclkl_sdncas) sdncas hold time 0 - t d(sdclkl_nbl) nbl valid time - 0.5 t h(sdclkl_nbl) nbl output time 0 - table 105. lpsdr sdram write timings (1) 1. guaranteed based on test during characterization. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t d(sdclkl _data ) data output valid time - 5 t h(sdclkl _data) data output hold time 2 - t d(sdclkl_add) address valid time - 2.8 t d(sdclkl-sdnwe) sdnwe valid time - 2 t h(sdclkl-sdnwe) sdnwe hold time 1 - t d(sdclkl- sdne) chip select valid time - 1.5 t h(sdclkl- sdne) chip select hold time 1 - t d(sdclkl-sdnras) sdnras valid time - 1.5 t h(sdclkl-sdnras) sdnras hold time 1.5 - t d(sdclkl-sdncas) sdncas valid time - 1.5 t d(sdclkl-sdncas) sdncas hold time 1.5 - t d(sdclkl_nbl) nbl valid time - 1.5 t h(sdclkl-nbl) nbl output time 1.5 -
electrical characteristics stm32f479xx 184/217 docid028010 rev 3 5.3.30 quad-spi in terface characteristics unless otherwise specified, the parameters given in table 106 and table 107 for quad-spi are derived from tests performed under the ambient temperature, f ahb frequency and v dd supply voltage conditions summarized in table xx, with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? measurement points are done at cmos levels: 0.5 v dd refer to section 5.3.20 for more details on the input/output alternate function characteristics. figure 73. quad-spi sdr timing diagram table 106. quad-spi characteristics in sdr mode (1) symbol parameter test co nditions min typ max unit f ck 1/t (ck) quad-spi clock frequency 2.7 v v dd 3.6 v, c l = 20 pf - - 90 mhz 1.71 v v dd 3.6 v, c l = 15 pf --84 t w(ckh) quad-spi clock high time \ t (ck) /2-1 - t (ck) /2 ns t w(ckl) quad-spi clock low time \ t (ck) /2 - t (ck) /2+1 t s(in) data input set-up time \ 0.5 - - t h(in) data input hold time \ 3- - t v(out) data output valid time \ -34 t h(out) data output hold time \ 2.5 - - 1. guaranteed based on test during characterization. 06y9 'dwdrxwsxw ' ' ' &orfn 'dwdlqsxw ' ' ' w &. w z&.+ w z&./ w u&. w i&. w v,1 w k,1 w y287 w k287
docid028010 rev 3 185/217 stm32f479xx electrical characteristics 190 figure 74. quad-spi ddr timing diagram 5.3.31 camera interface (d cmi) timing specifications unless otherwise specified, the parameters given in table 108 for dcmi are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage summarized in table 17 , with the following configuration: ? dcmi_pixclk polarity: falling ? dcmi_vsync and dcmi_hsync polarity: high ? data formats: 14 bits ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 v dd table 107. quad-spi characteristics in ddr mode (1) symbol parameter test conditions min typ max unit f ck 1/t (ck) quad-spi clock frequency 2.7 v v dd 3.6 v, c l = 20 pf --80 mhz 1.71 v v dd 3.6 v, c l = 15 pf --70 t w(ckh) quad-spi clock high time \ t (ck) /2-1 - t (ck) /2 ns t w(ckl) quad-spi clock low time - t (ck) /2 - t (ck) /2+1 t sr(in) t sf(in) data input set-up time 2.7 v v dd 3.6 v 2 - - 1.71 v v dd 3.6 v 0.5 - - t hr(in) t hf(in) data input hold time 2.7 v v dd 3.6 v 3 - - 1.71 v v dd 3.6 v 4.5 - - t vr(out) t vf(out) data output valid time dhhc=0 - 8 10.5 dhhc=1 pres=1,2? -t hclk /2+2 t hclk /2+2.5 t h(out) t f(out) data output hold time dhhc=0 7 - - dhhc=1 pres=1,2? t hclk /2+0.5 - - 1. guaranteed based on test during characterization. 06y9 'dwdrxwsxw ' ' ' &orfn 'dwdlqsxw ' ' ' w &. w z&.+ w z&./ w u&. w i&. w vi,1 w ki,1 w yi287 w ku287 ' ' ' ' ' ' w yu287 w ki287 w vu,1 w ku,1
electrical characteristics stm32f479xx 186/217 docid028010 rev 3 figure 75. dcmi timing diagram 5.3.32 lcd-tft controller (ltdc) characteristics unless otherwise specified, the parameters given in table 109 for lcd-tft are derived from tests performed under the ambient temperature, f hclk frequency and vdd supply voltage summarized in table 17 , with the following configuration: ? lcd_clk polarity: high ? lcd_de polarity: low ? lcd_vsync and lcd_hsync polarity: high ? pixel formats: 24 bits ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c l = 30 pf ? measurement points are done at cmos levels: 0.5 v dd table 108. dcmi characteristics (1) 1. 1.guaranteed based on test during characterization. symbol parameter min max unit - frequency ratio dcmi_pixclk/f hclk -0.4 - dcmi_pixclk pixel clock input - 54 mhz d pixel pixel clock input duty cycle 30 70 % t su(data) data input setup time 4 - ns t h(data) data input hold time 1 - t su(hsync) t su(vsync) dcmi_hsync/dcmi_vsync input setup time 3.5 - t h(hsync) t h(vsync) dcmi_hsync/dcmi_vsync input hold time 0 - 069 '&0,b3,;&/. w vx96<1& w vx+6<1& '&0,b+6<1& '&0,b96<1& '$7$>@ '&0,b3,;&/. w k+6<1& w k+6<1& w vx'$7$ w k'$7$
docid028010 rev 3 187/217 stm32f479xx electrical characteristics 190 figure 76. lcd-tft horizontal timing diagram table 109. ltdc characteristics (1) 1. based on test during characterization. symbol parameter min max unit f clk ltdc clock output frequency - 65 mhz d clk ltdc clock output duty cycle 45 55 % t w(clkh) t w(clkl) clock high time, low time t w(clk) /2 ? 0.5 t w(clk) /2+0.5 ns t v(data) data output valid time - 1.5 t h(data) data output hold time 0 - t v(hsync) hsync/vsync/de output valid time - 0.5 t v(vsync) t v(de) t h(hsync) hsync/vsync/de output hold time 0 - t h(vsync) th(de) 069 /&'b&/. wy+6<1& /&'b+6<1& /&'b'( /&'b5>@ /&'b*>@ /&'b%>@ w&/. /&'b96<1& wy+6<1& wy'( wk'( 1jyfm 1jyfm wy'$7$ wk'$7$ 1jyfm / +6<1& zlgwk +rul]rqwdo edfnsrufk $fwlyhzlgwk +rul]rqwdo edfnsrufk 2qholqh
electrical characteristics stm32f479xx 188/217 docid028010 rev 3 figure 77. lcd-tft vertical timing diagram 5.3.33 sd/sdio mmc card host in terface (sdio) characteristics unless otherwise specified, the parameters given in table 110 for the sdio/mmc interface are derived from tests performed under the ambient temperature, f pclk2 frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 v dd refer to section 5.3.20 for more details on the in put/output characteristics. figure 78. sdio high-speed mode 069 /&'b&/. wy96<1& /&'b5>@ /&'b*>@ /&'b%>@ w&/. /&'b96<1& wy96<1& -linesdata 96<1& zlgwk 9huwlfdo edfnsrufk $fwlyhzlgwk 9huwlfdo edfnsrufk 2qhiudph t 7#+( #+ $#-$ output $#-$ input t # t 7#+, t /6 t /( t )35 t )( t f t r ai
docid028010 rev 3 189/217 stm32f479xx electrical characteristics 190 figure 79. sd default mode ai #+ $#-$ output t /6$ t /($ table 110. dynamic characteristic s: sd / mmc characteristics, v dd = 2.7 to 3.6 v (1) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 8/3 - t w(ckl) clock low time f pp =50 mhz 9.5 10.5 - ns t w(ckh) clock high time 8.5 9.5 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs f pp =50 mhz 2.0 - - ns t ih input hold time hs 2.0 - - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs f pp =50 mhz -1313.5 ns t oh output hold time hs 12.5 - - cmd, d inputs (referenced to ck) in sd default mode t isud input setup time sd f pp =25 mhz 2.0 - - ns t ihd input hold time sd 2.5 - - cmd, d outputs (referenced to ck) in sd default mode t ovd output valid default time sd f pp =25 mhz -1.52.0 ns t ohd output hold default time sd 1.0 - - 1. guaranteed based on test during characterization.
electrical characteristics stm32f479xx 190/217 docid028010 rev 3 5.3.34 rtc characteristics table 111. dynamic characteristics: sd / mmc characteristics, v dd = 1.71 to 1.9 v (1)(2) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 8/3 - t w(ckl) clock low time f pp =50 mhz 9.5 10.5 - ns t w(ckh) clock high time 8.5 9.5 - cmd, d inputs (referenced to ck) in emmc mode t isu input setup time hs f pp =50 mhz 0.5 - - ns t ih input hold time hs 3.5 - - cmd, d outputs (reference d to ck) in emmc mode t ov output valid time hs f pp =50 mhz - 13.5 14.5 ns t oh output hold time hs 13.0 - - 1. guaranteed based on test during characterization. 2. c load = 20 pf. table 112. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write oper ation from/to an rtc register 4 -
docid028010 rev 3 191/217 stm32f479xx package information 215 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com. ecopack ? is an st trademark. 6.1 lqfp100 package information figure 80. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).'0,!.% $ $ $ % % % + ccc # # ,?-%?6 ! ! ! , , c b !
package information stm32f479xx 192/217 docid028010 rev 3 table 113. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0. 6220 0.6299 0.6378 d1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0. 6220 0.6299 0.6378 e1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031
docid028010 rev 3 193/217 stm32f479xx package information 215 figure 81. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. device marking for lqfp100 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 82. lqfp100 marking example (package top view) 1. samples marked "es" are to be considered as ?engineer ing samples?: i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. aic 069 670) 9,7 5 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh :: < 'dwhfrgh 3lqlghqwlilhu
package information stm32f479xx 194/217 docid028010 rev 3 6.2 lqfp144 package information figure 83. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 1. drawing is not to scale. h ,'(17,),&$7,21 3,1 *$8*(3/$1( pp 6($7,1* 3/$1( ' ' ' ( ( ( . fff & & $b0(b9 $ $ $ / / f e $
docid028010 rev 3 195/217 stm32f479xx package information 215 table 114. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.6890 - e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031
package information stm32f479xx 196/217 docid028010 rev 3 figure 84. lqfp144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. device marking for lqfp144 figure 85 gives an example of topside marking orientation versus pin 1 identifier location. figure 85. lqfp144 marking example (package top view) 1. samples marked "es" are to be considered as ?engineer ing samples?: i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. dlh 069 3lqlghqwlilhu 5 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 'dwhfrgh <:: 670)=,7
docid028010 rev 3 197/217 stm32f479xx package information 215 6.3 wlcsp168 package information figure 86. wlcsp168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale package outline $6b0(b9 h ) * h h %rwwrpylhz %xpsvlgh h $edooorfdwlrq ' $rulhqwdwlrq uhihuhqfh 7rsylhz :dihuedfnvlgh 'hwdlo$ $ $ 6lghylhz $ ( 'hwdlo$ 5rwdwhg? hhh %xps 6hdwlqj sodqh e $ $ fff ggg = = ; < = ddd ; = eee = ; <
package information stm32f479xx 198/217 docid028010 rev 3 table 115. wlcsp168 - 168-pin, 4.891 x 5.69 2 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.170 - - 0.0067 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating. - 0.025 - - 0.0010 - b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 4.856 4.891 4.926 0.1912 0.1926 0.1939 e 5.657 5.692 5.727 0.2227 0.2241 0.2255 e - 0.400 - - 0.0157 - e1 - 4.400 - - 0.1732 - e2 - 5.200 - - 0.2047 - f - 0.2455 - - 0.0097 - g - 0.246 - - 0.0097 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020
docid028010 rev 3 199/217 stm32f479xx package information 215 6.4 ufbga169 package information figure 87. ufbga169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not in scale. table 116. ufbga169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.1 10 0.0020 0.0031 0.0043 a2 0.400 0.450 0.50 0 0.0157 0.0177 0.0197 a3 - 0.130 - - 0.0051 - a4 0.270 0.320 0.37 0 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 6.950 7.000 7.050 0.2736 0.2756 0.2776 d1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e 6.950 7.000 7.050 0.2736 0.2756 0.2776 e1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e - 0.500 - - 0.0197 - $<9b0(b9 6hdwlqjsodqh $ $ $ h ) ) h 1 $ %277209,(: ( ' 7239,(: ?eedoov < ; < hhh ? 0 iii ? 0 = = ; $edoo lghqwlilhu $edoo lqgh[duhd e ' ( $ $ = = ggg 6,'(9,(:
package information stm32f479xx 200/217 docid028010 rev 3 device marking for ufbga169 the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 88. ufbga169 marking example (package top view) 1. samples marked "es" are to be considered as ?engineer ing samples?: i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. f 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 116. ufbga169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 06y9 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 3lq lghqwlilhu 'dwhfrgh z tt ^dd??& e?/,
docid028010 rev 3 201/217 stm32f479xx package information 215 6.5 lqfp176 package information figure 89. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package outline 1. drawing is not to scale. 4?-%?6 ! ! e % (% $ ($ :$ :% b mm gaugeplane ! , , k c )$%.4)&)#!4)/. 0). 3eatingplane # ! table 117. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 - 1.450 0.0531 - 0.0060 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 23.900 - 24.100 0.9409 - 0.9488 e 23.900 - 24.100 0.9409 - 0.9488
package information stm32f479xx 202/217 docid028010 rev 3 e - 0.500 - - 0.0197 - hd 25.900 - 26.100 1.0200 - 1.0276 he 25.900 - 26.100 1.0200 - 1.0276 l 0.450 - 0.750 0.0177 - 0.0295 l1 - 1.000 - - 0.0394 - zd - 1.250 - - 0.0492 - ze - 1.250 - - 0.0492 - ccc - - 0.080 - - 0.0031 k 0 - 7 0 - 7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 117. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
docid028010 rev 3 203/217 stm32f479xx package information 215 figure 90. lqfp176 recommended footprint 1. dimensions are expr essed in millimeters. 4?&0?6
package information stm32f479xx 204/217 docid028010 rev 3 device marking for lqfp176 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 91. lqfp176 marking example (package top view) 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. tt z ^??&e?//dh 'dwhfrgh 5hylvlrqfrgh 06y9 3lq lghqwlilhu 3urgxfwlghqwlilfdwlrq
docid028010 rev 3 205/217 stm32f479xx package information 215 6.6 ufbga176+25 package information figure 92. ufbga176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not to scale. table 118. ufbga176+2 5, - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.1 10 0.0020 0.0031 0.0043 a2 0.400 0.450 0.50 0 0.0157 0.0177 0.0197 a4 0.270 0.320 0.37 0 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 9.950 10.000 10.050 0.3917 0.3937 0.3957 e 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - f 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 zdzs ^?]vp?ov ? & & z ? kddkds/t dkws/t ?eedoov $ hhh ? 0 iii ? 0 & & $ & $edoo lghqwlilhu $edoo lqgh[ duhd e
package information stm32f479xx 206/217 docid028010 rev 3 figure 93. ufbga176+ 25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint table 119. ufbga176+25 recommended pcb design rules (0.65 mm pitch bga) dimension recommended values pitch 0.65 mm dpad 0.300 mm dsm 0.400 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.300 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.100 mm z&wzs 'sdg 'vp
docid028010 rev 3 207/217 stm32f479xx package information 215 6.7 lqfp208 package information figure 94. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package outline 1. drawing is not to scale. ' ' ' ( ( ( h / *$8*(3/$1( pp e & 6($7,1* 3/$1( fff & ,'(17,),&$7,21 3,1 f / $ $ $ $ 6)@.&@7 . table 120. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 -- - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106
package information stm32f479xx 208/217 docid028010 rev 3 c 0.090 - 0.200 0.0035 - 0.0079 d 29.800 30.000 30.200 1.1732 1.1811 1.1890 d1 27.800 28.000 28.200 1.0945 1.1024 1.1102 d3 - 25.500 - - 1.0039 - e 29.800 30.000 30.200 1.1732 1.1811 1.1890 e1 27.800 28.000 28.200 1.0945 1.1024 1.1102 e3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0 3.5 7.0 0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 120. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
docid028010 rev 3 209/217 stm32f479xx package information 215 figure 95. lqfp208 recommended footprint 1. dimensions are expr essed in millimeters. -36
package information stm32f479xx 210/217 docid028010 rev 3 device marking for lqfp208 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 96. lqfp208 marking example (package top view) 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 06y9 3lq lghqwlilhu tt z ^dd??&e?/d 'dwhfrgh 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq
docid028010 rev 3 211/217 stm32f479xx package information 215 6.8 tfbga216 package information figure 97. tfbga216 - thin fine pitch ball grid array 13 13 0.8mm, package outline 1. drawing is not to scale. $/b0(b9 6hdwlqjsodqh $ h ) ) ' 5 ?eedoov $ ( 7239,(: %277209,(: h $ $ < ; = ggg = ' ( hhh = < ; iii ? ? 0 0 = $edoo lghqwlilhu $edoo lqgh[duhd table 121. tfbga216 - thin fine pitch ball grid array 13 13 0.8mm package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.100 - - 0.0433 a1 0.150 - - 0.0059 - - a2 - 0.760 - - 0.0299 - a4 - 0.210 - - 0.0083 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 12.850 13.000 13.150 0.5118 0.5118 0.5177 d1 - 11.200 - - 0.4409 - e 12.850 13.000 13.150 0.5118 0.5118 0.5177 e1 - 11.200 - - 0.4409 - e - 0.800 - - 0.0315 - f - 0.900 - - 0.0354 - ddd - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package information stm32f479xx 212/217 docid028010 rev 3 device marking for tfbga216 the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 98. tfbga216 marking example (package top view) 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 06y9 'dwhfrgh z tt 5hylvlrqfrgh ^??& 3urgxfwlghqwlilfdwlrq %doo lghqwlilhu e?e/,h
docid028010 rev 3 213/217 stm32f479xx package information 215 6.9 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 122. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp100 43 c/w thermal resistance junction-ambient lqfp144 40 thermal resistance junction-ambient wlcsp168 31 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient lqfp208 - 28 28 mm / 0.5 mm pitch 19 thermal resistance junction-ambient ufbga169 - 7 7mm / 0.5 mm pitch 52 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.5 mm pitch 39 thermal resistance junction-ambient tfbga216 - 13 13 mm / 0.8 mm pitch 29
part numbering stm32f479xx 214/217 docid028010 rev 3 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 123. ordering information scheme example: stm32 f 479 v i t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 479= stm32f479xx, usb otg fs/hs, camera interface, ethernet, lcd-tft, dsihost, cryptographic acceleration, quad-spi, chrom-art graphical accelerator. pin count v = 100 pins z = 144 pins a = 168 and 169 pins i = 176 pins b = 208 pins n = 216 pins flash memory size g = 1024 kbytes of flash memory i = 2048 kbytes of flash memory package t = lqfp h = bga y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel
docid028010 rev 3 215/217 stm32f479xx recommendations when using internal reset off 215 appendix a recommendations wh en using internal reset off when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry must be disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and vbat pin should be connected to v dd . ? the over-drive mode is not supported. a.1 operating conditions table 124. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum flash memory access frequency with wait states (1)(2) 1. applicable only when the code is executed from flas h memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. i/o operation possible flash memory operations v dd =1.7 to 2.1 v (3) 3. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 2.19.1: internal reset on ). conversion time up to 1.2 msps 20 mhz (4) 4. prefetch is not available. refer to an3430 applic ation note for details on how to adjust performance and power. 168 mhz with 8 wait states and over-drive off ? no i/o compensation 8-bit erase and program operations only
revision history stm32f479xx 216/217 docid028010 rev 3 8 revision history table 125. document revision history date revision changes 01-sep-2015 1 initial release. 19-oct-2015 2 updated table 4: regulator on/off and internal reset on/off availability and table 54: emi characteristics . updated figure 17: stm32f47x ufbga176 ballout , figure 35: pll output clock waveforms in center spread mode and figure 36: pll output clock waveforms in down spread mode . updated title of section 6.8: tfbga216 package information . 08-mar-2016 3 updated cover page with introduction of lqfp100 and lqfp144 packages. updated section 1: description and section 1.1: compatibility throughout the family . updated figure 1: incompatible board design for lqfp176 package and its footnote. updated table 1: device summary , table 2: stm32f479xx features and peripheral counts , table 4: regulator on/off and internal reset on/off availability , table 10: stm32f479xx pin and ball definitions , table 11: fmc pin definition , table 12: alternate function , table 17: general operating conditions , table 55: esd absolute maximum ratings , table 76: adc characteristics , table 122: package thermal characteristics and table 123: ordering information scheme . removed former table 73: ethernet dc electrical characteristics . added figure 13: stm32f47x lqfp100 pinout and figure 14: stm32f47x lqfp144 pinout . updated figure 17: stm32f47x ufbga176 ballout , figure 18: stm32f47x lqfp176 pinout and figure 33: acchsi vs. temperature . added section 6.1: lqfp100 package information and section 6.2: lqfp144 package information . replaced former footnote 7 of table 10: stm32f479xx pin and ball definitions with footnote 2 . added footnote 3 to table 14: voltage characteristics . updated footnote 1 of figure 56 and footnote 1 of figure 57 .
docid028010 rev 3 217/217 stm32f479xx 217 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved

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